ADSP-BF609 - MCU RAM initialization

Hello ,

This is regarding L2 RAM initialization.

When I try to initialize/write into L2 bank memory in core1, I get exception for last three bank access.

It is because those areas are having "CPLB_READONLY_ACCESS" tags.When I modified it to "CACHE_MEM_MODE" it works fine.

Code is as shown below:

For Core 1
{0xC8080000, (ENUM_DCPLB_DATA_64KB | CPLB_DNOCACHE)},
   {0xC8090000, (ENUM_DCPLB_DATA_64KB | CPLB_READONLY_ACCESS)},
   {0xC80A0000, (ENUM_DCPLB_DATA_16KB | CPLB_READONLY_ACCESS)},
   {0xC80A4000, (ENUM_DCPLB_DATA_16KB | CPLB_READONLY_ACCESS)},
   {0xC80A8000, (ENUM_DCPLB_DATA_16KB | CACHE_MEM_MODE)},
   {0xC80AC000, (ENUM_DCPLB_DATA_16KB | CACHE_MEM_MODE)},
   {0xC80B0000, (ENUM_DCPLB_DATA_64KB | CACHE_MEM_MODE)},

After change
   {0xC8080000, (ENUM_DCPLB_DATA_64KB | CPLB_DNOCACHE)},
   {0xC8090000, (ENUM_DCPLB_DATA_64KB | CACHE_MEM_MODE)},
   {0xC80A0000, (ENUM_DCPLB_DATA_16KB | CACHE_MEM_MODE)},
   {0xC80A4000, (ENUM_DCPLB_DATA_16KB | CACHE_MEM_MODE)},
   {0xC80A8000, (ENUM_DCPLB_DATA_16KB | CACHE_MEM_MODE)},
   {0xC80AC000, (ENUM_DCPLB_DATA_16KB | CACHE_MEM_MODE)},
   {0xC80B0000, (ENUM_DCPLB_DATA_64KB | CACHE_MEM_MODE)},

Is it fine to modify app_cplbtab.c ??

Thanks,

Jayapriya

  • Hi Jayapriya,

    Ensure that you have enabled the option "Permit alteration of CPLB table entries", by opening the system.svc file for your project, and going to the 'Startup Code/LDF' tab. This will add $VDSG tags in your app_cplbtab.c file, which will ensure that any changes you make are preserved.

    If you do not enable this option, any modifications you make will be discarded when the System Builder regenerates these files.

    Regards,

    Craig.

  • 0
    •  Analog Employees 
    on Aug 2, 2018 4:53 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

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    EZ Admin