hello, i want to transmit data through eppi2 with internal clock and sync, but my code could't get correct result.
my code is like this:
void EPPI2_CH0_HANDLER(uint32_t iid, void *handlerArg)
*pREG_DMA31_STAT = ENUM_DMA_STAT_IRQDONE;
*pREG_EPPI2_CTL = ENUM_EPPI_CTL_PACK_EN | //pack enable
ENUM_EPPI_CTL_SWAP_EN | //fist data on MSB data
ENUM_EPPI_CTL_DLEN08 | //8bit transmit
ENUM_EPPI_CTL_FS1HI_FS2HI | //data valid on high level
ENUM_EPPI_CTL_POLC11 | //sample data and sync signal on rising edge
ENUM_EPPI_CTL_SYNC2 | // 2 FS mode
ENUM_EPPI_CTL_INTFS | // internal frame sync
ENUM_EPPI_CTL_INTCLK | // internal clock
ENUM_EPPI_CTL_NON656 | // GP mode
ENUM_EPPI_CTL_TXMODE; // transmit mode (write memory)
*pREG_EPPI2_CLKDIV = 0x3;
*pREG_EPPI2_LINE = COL;
*pREG_EPPI2_FRAME = ROW;
*pREG_DMA31_ADDRSTART = (void*)g_txBuffer;
*pREG_DMA31_XCNT = COL / 32;
*pREG_DMA31_XMOD = 32;
*pREG_DMA31_YCNT = ROW;
*pREG_DMA31_YMOD = 32;
*pREG_DMA31_CFG = ENUM_DMA_CFG_MSIZE32 | ENUM_DMA_CFG_PSIZE04
| ENUM_DMA_CFG_ADDR2D | ENUM_DMA_CFG_YCNT_INT | ENUM_DMA_CFG_SYNC
| ENUM_DMA_CFG_READ | ENUM_DMA_CFG_AUTO;
adi_int_InstallHandler(INTR_EPPI2_CH0_DMA, EPPI2_CH0_HANDLER, 0, true);
*pREG_DMA31_CFG |= ENUM_DMA_CFG_EN;
*pREG_EPPI2_CTL |= ENUM_EPPI_CTL_EN;
*pREG_DMA31_CFG &= ~ENUM_DMA_CFG_EN;
*pREG_EPPI2_CTL &= ~ENUM_EPPI_CTL_EN;
adi_pwr_Init(25 * MHZTOHZ, 500 * MHZTOHZ, 125 * MHZTOHZ, 72 * MHZTOHZ);
when i call enableEPPI2 function after init ppi and dma, the dma didn't send data to peripheral device.
Since your question relates to BF609, I have moved it to the BF60x subcommunity of Blackfin Processors community. Please continue the discussion here.
Engineer Zone Moderator
The first thing I can notice is that, you are using 2FS mode with intenal Frame sync generation setting. But you are not configuring EPPI registers to configure Frame syncs. Refer HRM for more details.
now i add code as fllow to set fs1 and fs2,
*pREG_EPPI2_FS1_WLHB = COL;
*pREG_EPPI2_FS1_PASPL = COL * 6;
*pREG_EPPI2_FS2_WLVB = ROW * (COL * 6);
*pREG_EPPI2_FS2_PALPF = ROW * COL * 12;
when i start the program, fs1 and fs2 is always out put waves, even if the dma did not work.
in this way, how the recieve device can assert when to recieve data.
If DMA is not getting started, do you see any error in the DMA status register? One thing I suspect is that, buffer submitted to DMA is not properly aligned as per the MSIZE configuration. You are using MSIZE=32 bytes (20H), so your buffer should aligned to 32-byte boundry. e.g. at address 0x00, or 0x20, or 0x40....so on.
I think, you can make sure that by adding following pragma before buffer defination.
#pragma align 32
unsigned char Tx_BUFF[BUFF_SIZE];
have you completed it? if not ,you can try: change ENUM_EPPI_CTL_DLEN08 to ENUM_EPPI_CTL_DLEN16, Even if your hardware is in 8bit mode. i met the similar.