I have the following settings in TX descriptor.
TDES0_CIC = 11 for every packet I send.
and also configured DMA_OPMODE in store and forward mode (TSF = 1) but still hardware doesn't insert checksum.
Also checked the TDES0_ER bit as status for any IP header/payload errors but its not set.
Do I have to configure more settings for Transmit checksum engine to be enabled?
Platform: BF609 EZ-Kit
Thanks and Regards,
Bharat Kumar Bacha.
Solved this issue by introducing delays 8 cycles of 50 MHz RMII clock between two successive writes to Operation Mode register.