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Accessing external lpddr sdram

Platform cross core

Accessing external lpddr sdram 256mb

Can't access the location of the sdram starting from 0 to 0x0fffffffh , using a pointer

Error:

A non recoverable error or exception has occurred

Description:  a data cplb miss has occurred without a corresponding cplb entry.

After the error came checked sequencer stat register, 0x26 error code

Parents
  • Hi,

    This exception occurs because you do not have a valid CPLB entry for the region of memory that you are accessing. When the Blackfin processor issues a memory operation for which no valid CPLB (cacheability protection lookaside buffer) descriptor exists in an MMR pair, an exception occurs. This exception places the processor into Supervisor mode and vectors to the MMU exception handler.

    If you are using CPLBs, it is necessary that you have a valid CPLB entry defined for every memory region that you access (you need not enable cache though). In case you access a memory that does not have a valid CPLB entry, you will get this exception.

    We recommend checking your cache protection options. Double click the "System.svc", navigate to the 'Startup Code/LDF' tab. In the 'Startup Code' tab there are options for Instruction and Data Cache - enable or disable these as required.

    Another possible cause of the CPLB miss without replacement in your program could be the use of an invalid address, or when there is a NULL pointer.

    It seems that you are using DDR in your project. Can you confirm whether you have enabled SDRAM in your application? There might be a chance that the variable is not correctly mapped to SDRAM memory space. To enable external memory, please navigate as follows.
    Open your project in CCES.->System.svc->LDF->External Memory-> Check "Use External memory(SDRAM)"

    Also make sure that the CPLB table covers the external memory space.

    Regards,
    Anand Selvaraj.

Reply
  • Hi,

    This exception occurs because you do not have a valid CPLB entry for the region of memory that you are accessing. When the Blackfin processor issues a memory operation for which no valid CPLB (cacheability protection lookaside buffer) descriptor exists in an MMR pair, an exception occurs. This exception places the processor into Supervisor mode and vectors to the MMU exception handler.

    If you are using CPLBs, it is necessary that you have a valid CPLB entry defined for every memory region that you access (you need not enable cache though). In case you access a memory that does not have a valid CPLB entry, you will get this exception.

    We recommend checking your cache protection options. Double click the "System.svc", navigate to the 'Startup Code/LDF' tab. In the 'Startup Code' tab there are options for Instruction and Data Cache - enable or disable these as required.

    Another possible cause of the CPLB miss without replacement in your program could be the use of an invalid address, or when there is a NULL pointer.

    It seems that you are using DDR in your project. Can you confirm whether you have enabled SDRAM in your application? There might be a chance that the variable is not correctly mapped to SDRAM memory space. To enable external memory, please navigate as follows.
    Open your project in CCES.->System.svc->LDF->External Memory-> Check "Use External memory(SDRAM)"

    Also make sure that the CPLB table covers the external memory space.

    Regards,
    Anand Selvaraj.

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