ADSP SC582 - UART0 auto buffer DMA - DMA somehow works but UART0 THR receives wrong data

Hi,

I am configuring UART0 with DMA and auto buffer. The DMA works so far, that it iterates through the memory, which it has to access.

However, the UART0 transmit shift register does not get the right data.

Does any one have an idea what might be wrong? Do I have to configure the SCB or CGU additionally?

Thx and best regards

exception

#define TX_SIZE (100)
#define RX_SIZE (100)

uint8_t txBuf[TX_SIZE];
uint8_t rxBuf[RX_SIZE];

void Uart0_Init_DMA(void){
	txBuf[0] = 0x41;
	for(int i = 0; i<16; i++){
		txBuf[i] = 0x41+i;
	}
	rxBuf[0] = 0x57;
	for(int i = 0; i<16; i++){
			rxBuf[i] = 0x57+i;
		}

	// Enable system protection unit for UART0 tx and rx master and slave
	*pREG_SPU0_SECUREP82 = 0x3; // rx
	*pREG_SPU0_SECUREP83 = 0x3; // tx

	// Configure UART0
	//Uart0_Mode(Uart0_Speed, Uart0_Parity_NONE, Uart0_Stop_1bit);
	*pREG_PORTC_FER_SET |= (1<<14)|(1<<13); 	// change gpio to pheripheral
	*pREG_UART0_CLK = 19200;//(u32)( ((f32)SCLK0_0 / (16.0 /*Default prescaler*/ * (f32)19200)) + 0.5 );
	*pREG_UART0_IMSK_SET = ENUM_UART_IMSK_ETBEI_LO | ENUM_UART_IMSK_ERBFI_LO;	// Make sure that ETBEI and ERBFI bit are cleared before configuring the DMA
	*pREG_UART0_CTL 	 = ENUM_UART_CTL_WL8BITS | ENUM_UART_CTL_CLK_EN;


	// Configure DMA tx
	*pREG_DMA20_CFG = (ENUM_DMA_CFG_READ | ENUM_DMA_CFG_MSIZE01 | ENUM_DMA_CFG_PSIZE01 | ENUM_DMA_CFG_AUTO | ENUM_DMA_CFG_STOP);
	*pREG_DMA20_XCNT = TX_SIZE-1;
	*pREG_DMA20_XMOD = 1;
	*pREG_DMA20_ADDRSTART = (void*) txBuf; // buffer array
	*pREG_DMA20_CFG |= ENUM_DMA_CFG_EN;

	// Configure DMA rx
	*pREG_DMA21_CFG = (ENUM_DMA_CFG_WRITE | ENUM_DMA_CFG_MSIZE01 | ENUM_DMA_CFG_PSIZE01 | ENUM_DMA_CFG_AUTO | ENUM_DMA_CFG_STOP);
	*pREG_DMA21_XCNT = RX_SIZE-1;
	*pREG_DMA21_XMOD = 1;
	*pREG_DMA21_ADDRSTART = (void*) rxBuf;
	*pREG_DMA21_CFG |= ENUM_DMA_CFG_EN;


	// Set ETBEI and ERBFI to start the transfer
	*pREG_UART0_IMSK_SET = ENUM_UART_IMSK_ERBFI_HI;
	*pREG_UART0_IMSK_SET = ENUM_UART_IMSK_ETBEI_HI;

}



fixed typo
[edited by: exception at 1:24 PM (GMT 0) on 27 Feb 2020]