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ADSP-CM403F Production
The ADSP-CM403F Mixed-Signal Control Processor integrates dual high precision 16 bit ADCs and an ARM® Cortex-M4™ processor core with floating-point unit...
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ADSP-CM403F on Analog.com

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ADC sampling rate



		

			

									
					    Fanacademia01
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Oct 28, 2024 
				
			
			
		
    

				
		
    
		    		    
		    
		    		      		            		        
    Category: Hardware
    
    		        		            		    
    Product Number:  ADSP-CM403F  
    
    		        		    		    	
			
    Hi everyone.
    

    I'm running the ADC Circular example to get familiar with the ADC and i had read the Hardware reference and the EE365 but i can't figure out how to change the sample rate.
    

    I'm using a 1 kHz tone as test signal and System View from Elanix to get the sampled signal and recontruct it.
    

    1.- If i change the SYSCLK from 96 MHz to, say, 90 MHz, the samples seem to be at correct timing, but if i use 100 MHz, the sampled frequency is totally off.
    

    2.- How can i calculate the sample rate (or even better, change it) for that example?
    

    Btw, it seems the sampling frequency is SYSCLK/NUMSAMPLES = 96 MHz/1000 = 96 kHz
    

    3.- I've tried to change the tcscs, tcsck and NCK without any change on the sampled signal.
    

    Thanks in advance.
    
									
			        
		
    

				
						
        

    
    Tags: 
                                            
                 hardware
                
                                                    
                 CM4xx Mixed-Signal Control Processors
                
                                                    
                 ADSP-CM403F
                
                                                    
                 microcontrollers
                
                                
            
    
    
    

		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    
















    
	
    
	
    
					



			


				
	









	
      
	

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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Oct 30, 2024 4:18 AM
            
            
					
      
	
      

		
		
      
					
      Hi,
      

      We are checking on this and we will get back to you as soon as possible.
      

      Regards,
      Nandini C
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
				
						
						
				
				
		
		
      
			
		
      
	
      

      

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                on Nov 2, 2024 8:54 PM
            
            
												
						in reply to NandiniC
					
									
        
	
        

		
		
        
					
        Hi, thanks. I've worked out one of the issues. SYSCLK and CORECLK has to be multiples, i mean, zero remainder, otherwise the example will approach the best multiples and get a coefficient. If that happens, the sampling rate on ADC behaves erratic.
        

        Having solved that, i'm still wandering how to change the sample rate of the ADC without having to change the SYSCLK frequency.
        

        Again, thanks in advance.
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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                on Nov 8, 2024 7:45 PM
            
            
					
          
	
          

		
		
          
					
          UPDATE: i've managed to change the sampling rate. To do so, you need to change the period of the GP timer. The sampling rate of the ADC comes out from the division between the sistem clock (SYSCLK) and the GP Timer period (PER). From my point of view, it doesn't make any sense, since the GP Timer provides the trigger source for the ADC and is not part of the ADCC. Besides, this isn't mentioned in any of the documents (Datasheet or HW reference). The only logical explanation i can think of is that the samples are equally spaced along the period of the GP Timer at SYSCLK rate.
          
			
          

		
			
	      

		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

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