Hi everyone,
I would like to configure the General-Purpose Counter (CNT) as "Zero Marker / push button support" in such a way that and interrupt service routine (ISR) is triggered with a rising edge of a square signal connected to the CNT1_ZM pin (PB_03 that corresponds to pin 38/74 of the expansion board).
I have followed the instructions of the "ADSP-CM40x Mixed-Signal Control Processor with ARM Cortex_M4 Hardware Reference (Preliminary Revision 0.2, September 2013)" sections:
- GP Counter General Programming Flow
- Configuring GP Counter Push-Button Operation
I have declared a variable "a" inside the ISR that must be incremented every time the ISR is triggered, if I run the program the value of a is always 0. I connected a square signal of 850Hz to both: pin 38 and 74. It did not work.
Can someone check the code below? I am not sure if the ISR is properly coded.
I am testing the code with a ADSP CM403 board and the analog and digital expansions boards.
You will find attached a pdf with the problem description.
Thank you very much in advance.
The configuration of the peripheral is as follows:
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*pREG_CNT1_CMD = BITM_CNT_CMD_W1LMAXZERO | BITM_CNT_CMD_W1LMINZERO | BITM_CNT_CMD_W1LCNTZERO |BITP_CNT_CMD_W1ZMONCE ;
*pREG_CNT1_IMSK = ENUM_CNT_IMSK_CZME_UMSK;
*pREG_CNT1_CFG = ENUM_CNT_CFG_NO_INPDIS | ENUM_CNT_CFG_CNTMODE_QUADENC | /* Enable input; Use quadrature counter mode */
ENUM_CNT_CFG_BNDMODE_BINENC | ENUM_CNT_CFG_ZMZC_DIS | /* Zero counter on ZM; ZM disabled (setting of BNDMODE has no effect) */
ENUM_CNT_CFG_CZMINV_AHI | /* Active high ZM (not used) */
ENUM_CNT_CFG_CUDINV_AHI | ENUM_CNT_CFG_CDGINV_AHI | /* Active high CUD and CDG */
ENUM_CNT_CFG_DEBDIS | ENUM_CNT_CFG_CNTDIS; /* Disable debounce; Disable counter */
adi_int_InstallHandler((IRQn_Type)INTR_CNT1_STAT, CNT1_STAT_ISR, 0, true);
NVIC_SetPriority((IRQn_Type)INTR_CNT1_STAT, 1); /* NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) */
NVIC_EnableIRQ((IRQn_Type)INTR_CNT1_STAT);
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And the interrupt service routine:
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void CNT1_STAT_ISR(uint32_t iid, void* handlerArg){
if (*pREG_CNT1_STAT &= BITM_CNT_IMSK_CZME){
*pREG_CNT1_STAT = 0x200;
a++; // a should increment every time the ISR is triggered
}
}
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