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Minimum SCLK in ADSP-21562

Category: Hardware

Hi

What is the minimum SCLK for the ADSP-21562, I can work with?

Can I program fCCLK to 200 or 100 MHz in ADSP-2156x processors

best George

  • Hi George,

    Please refer the Clock Operating Conditions (table: 19) to know about minimum SCLK for the ADSP-21562 in datasheet (Pg No: 46). The link is given below.
    www.analog.com/.../adsp-21562-21563-21565-21566-21567-21569.pdf

    Regarding "Can I program fCCLK to 200 or 100 MHz in ADSP-2156x processors"
    As per the datasheet, ADSP-2156x supports Core Clock (CCLK) Frequency of (400Mhz to 1000Mhz). So, we cannot guarantee the proper operation of the devices if the specification not followed.

    Regards,
    Anand Selvaraj.

  • Hi
    I'm a bit confused with some timing specifications in the ADSP-2156x datasheet.

    1. As per the datasheet (Table 1 Pg No:4) maximum Core Clock Frequency for the ADSP-21562 is 400 MHz.
    On the other side Table 19 (Pg No:46) says that the minimum CCLK is 400 MHz also.
    This means that the only valid CCLK frequency for the ADSP-21562 Processor is 400 MHz. Is it true?

    2. Table 20 of the datasheet limits PLL Clock Frequency to 1.2 - 2.00 GHz.
    Table 33 of the datasheet limits SYS_CLKIN0 Frequency to 20 - 30 MHz.
    As per Table 2-13 (Pg No:2-24) of the ADSP-2156x SHARC+ Processor Hardware Reference the default CGU_DIV.CSEL bit field value is 3 for 400/600 MHz CCLK processor variants and the default multiplier
    value (MSEL) is 40 for 400 MHz CCLK (Table 2-12 Pg No:2-21).
    This means that the only valid SYS_CLKIN0 frequency for the ADSP-21562 Processor is 30 MHz. Is it true?

    Thank You

    Regards,
    George

  • Hi George,

    Regarding question 1,
    >>>> Yes, As per the datasheet in (Table 1 Pg No:4) maximum Core Clock Frequency is given for the specific processors. On the other side Table 19 (Pg No:46) is given for ADSP-2156x family of processors. So, the maximum Core Clock Frequency for the ADSP-21562 is 400 MHz.

    Regarding Question 2,
    >>>> As per the datasheet of Table 33, the supported  SYS_CLKIN0 Frequency is  lies between 20 - 30 MHz. The ADSP-2156x EZ-Kit processors support 25MHz of SYS_CLKIN0 .

    Regarding "As per Table 2-13 (Pg No:2-24) of the ADSP-2156x SHARC+ Processor Hardware Reference the default CGU_DIV.CSEL bit field value is 3 for 400/600 MHz CCLK processor variants and the default multiplier value (MSEL) is 40 for 400 MHz CCLK (Table 2-12 Pg No:2-21).
    >>>> These points are applicable when the processor come out of reset. The CGU allows programs to change the  SYSCLK frequency by writing values to the CGU_DIV register.

    Regards,
    Anand Selvaraj.