Dear ADI engineers:
Currently, when we designs an audio system with ADI SHARC+ DSP, we met a puzzled problem. The basic system block is as below:
Here, the audio source is driven by an A2B master(such as HU) by A2B_1 above. Besides that, we have another A2B (A2B_2 in the diagram above) for the data acquisition of MICs or other signals, in which case SHARC+ act as the Host IC，A2B_2 as the A2B master and MICs act as the slave.
As you see, the clock for A2B_1 is marked as red, which is provided by the master; while the clock for A2B_2 is marked as green, which is provided by SHARC+. To make the clock be synchronous between A2B_1 and A2B_2, the simple way is to use A2B_1’s clock to drive A2B_2’s clock inside SHARC+. But we don’t want to do as that, because it may make all the DSP audio processes (including A2B_2) depend too much on A2B_1, which will limit the extendibility and flexibility of our system.
Another possible option for us is to use ASRC units inside SHARC+. But according to the chip specification, there are only 4 ASRC units for the input signals, which can make up a daisy-chain for the input TDM stream. And totally, we can process 8 TDM slots at most. And as you known, the input audio stream is with 16 TDM slots, which has exceeded the maximum ASRC capability. So it seems this solution is also infeasible.
Since both A2B and SHARC+ are ADI products, we wish you can help us to give some suggestions.