The clock synchronous issue for inputs & outputs signals of SHARC+ 2156x

Hi,

1) Regarding,"Here, the audio source is driven by an A2B master(such as HU) by A2B_1 above. Besides that, we have another A2B (A2B_2 in the diagram above) for the data acquisition of MICs or other signals, in which case SHARC+ act as the Host IC，A2B_2 as the A2B master and MICs act as the slave. "
>>   In A2B, By default Host will provide clock for A2B master,slave and slave connected peripherals. Once all the A2B connected Master and slave nodes are discovered.
>>   All the A2B slave and A2B master are connected in line topology with Host. They are connected in daisy chain through a A2B cable(twisted pair).
>>   Can you explain the setup? Which one is master here A2B_1 or A2B_2?
>>   Are the A2B_1 and A2B_2 are individually interfaced with different ADSP-21565 SPORT channel like audio codec or is it connected with A2B bus?

2) Regarding,"Here, the audio source is driven by an A2B master(such as HU) by A2B_1 above. Besides that, we have another A2B (A2B_2 in the diagram above) for the data acquisition of MICs or other signals,in which case SHARC+ act as the Host IC，A2B_2 as the A2B master and MICs act as the slave."
>> Is ADSP-21565 is acting as a host or local processor connected to a Subordinate Node.

3) Regarding,"To make the clock be synchronous between A2B_1 and A2B_2, the simple way is to use A2B_1’s clock to drive A2B_2’s clock inside SHARC+. But we don’t want to do as that, because it may make all the DSP audio processes (including A2B_2) depend too much on A2B_1, which will limit the extendibility and flexibility of our system."
>> The Host provided bitclk and FS can be routed to ADSP-21565 using DAI SRU config and same clock can be used by A2B_2 also.

4)  Regarding,"As you see, the clock for A2B_1 is marked as red, which is provided by the master;
>>  How the master is getting bit clock and FS without Host?

Regards,
Anand Selvaraj.

Thanks Anand Selvaraj!
[In A2B, By default Host will provide clock for A2B master,slave and slave connected peripherals. Once all the A2B connected Master and slave nodes are discovered.]
->Understood.

[All the A2B slave and A2B master are connected in line topology with Host. They are connected in daisy chain through a A2B cable(twisted pair).]
->Understood

[Can you explain the setup? Which one is master here A2B_1 or A2B_2?]
-> Here, A2B_1 and A2B_2 are two different A2B daisy chain. For A2B_1, the host master maybe a HU, which should provide the bck & FS clock of A2B_1 chain. And for A2B_2, ADSP-21565 act as the host master, and MICs/sensors act as the slave.

[Are the A2B_1 and A2B_2 are individually interfaced with different ADSP-21565 SPORT channel like audio codec or is it connected with A2B bus?]
->Yes, A2B_1 and A2B_2 are individually interfaced with different ADSP-21565 SPORT channel.

[Is ADSP-21565 is acting as a host or local processor connected to a Subordinate Node.]
->For A2B_1, ADSP-21565 acts as a local processor connected to a Subordinate Node. For A2B_2, ADSP-21565 acts as a host master.

[The Host provided bitclk and FS can be routed to ADSP-21565 using DAI SRU config and same clock can be used by A2B_2 also.]
-> Yes, this is the same as what we do now. But I think it will limit the extendibility and flexibility of our system. So I want to know if there is any better solutions/designs for the system.

[How the master is getting bit clock and FS without Host?]
->For A2B_1, the host master maybe a HU which is missed out in the diagram. The HU should locate at the left side in the block. For A2B_2, the host master is ADSP-21565. its BCK & FS should be provided either by ADSP-21565 internal clock or by the external clock(from A2B_1). We wish it should be provided by ADSP-21565 internal clock. But we don't know how to solve the clock synchronous issue between A2B_1 and A2B_2.

Hi,

1) Regarding,"Yes, this is the same as what we do now. But I think it will limit the extendibility and flexibility of our system. So I want to know if there is any better solutions/designs for the system."
>> Are you getting any issues?
>> Are the A2B_1 and A2B_2 working at different frame sync rates?

2)Regarding,"For A2B_1, the host master maybe a HU which is missed out in the diagram. The HU should locate at the left side in the block. For A2B_2, the host master is ADSP-21565. its BCK & FS should be provided either by ADSP-21565 internal clock or by the external clock(from A2B_1). We wish it should be provided by ADSP-21565 internal clock. But we don't know how to solve the clock synchronous issue between A2B_1 and A2B_2."
>>If A2B_1 and A2B_2 both are working individually(not connected through A2B bus daisy chain) or A2B_1 master is not controlling(no upstream/downstream communication between A2B_1 and A2B_2) A2B_2 slave, then
  Can you try with PCG from ADSP-21565 to A2B_2?

Regards,
Anand Selvaraj.