hardly to find in hardware reference. What is the maximum SCLK, I can work with?
Please refer the maximum SCLK value in the data sheet(Pg No: 46).
Dear Anand, thks... as far as I read, the maximum Timer frequency using continuous PWM-Mode is dedicated to SCLK0. So, does this mean that I can drive a ADC-Clock with 125MHz provided by a Timer pin. 125MHz is the maximum frequency I can adjust with 21569. A answer would be great, because an circuit design depends on this information,
Apologies for the delay in response.
The maximum frequency possible to generate on the TIMER_TMR[nn] pin is achieved by setting TIMER_TMR[n]_PER to 2 and TIMER_TMR[n]_WID to 1. This operation makes the TIMER_TMR[nn] pin toggle each SCLK clock cycle (assuming the timer is configured to clock internally), producing a duty cycle of 50%.
So, you can generate 62.5 MHz on the TIMER_TMR[nn] pin with the maximum SCLK0 frequency (125Mhz).