I'm trying to use SPI0 on the ADSP-21569 in master mode to configure an external chip.
#define SPI0_SLVSEL (ENUM_SPI_SLVSEL_SSEL1_HI | ENUM_SPI_SLVSEL_SSEL1_EN);
#define SPI0_TX_ENABLE (ENUM_SPI_TXCTL_TX_EN | ENUM_SPI_TXCTL_TTI_EN)
#define SPI0_CTL (ENUM_SPI_CTL_EN | ENUM_SPI_CTL_MASTER | ENUM_SPI_CTL_SIZE08 | ENUM_SPI_CTL_HW_SSEL)
#define EXT_CMD_RESET (0xFF)
.... //init SLVSEL, TXCTL, CTL
ustat1 = EXT_CMD_RESET;
dm(REG_SPI0_TFIFO) = ustat1;
The data is transmitted correctly and the chip select works also as expected with ASSEL=1;
But I do not get an information when the SPI transfer is really finished.
I'm not talking about empty TX FIFO flag etc and I do not want to use DMAs and IRQs for this.
I just need the information when the transfer was done on the pins and the SPI controller has released the CS (SPI0_SEL1) to high.
In older SHARCs I've used the SPIF flag in the status register but none of the status register bits is changing with this operation.
[edited by: ChristianH at 5:34 AM (GMT -4) on 16 Aug 2021]