//************************************************
//**************** InitPLL.asm *******************
//************************************************
#include <def21479.h>
//#define PLLD4_SDCKR4 // Uncomment if final PLLD=SDCKR=4..
.global InitPLL;
.extern start;
.section/pm seg_pmco;
InitPLL:
// PLL Programming Sequence by ODemirci
// CLKIN=16.625MHz for ADSP-21479 EZ-KIT
// FCCLK=(CLKIN*2*PLLM)/(PLLD*D) where INDIV=0-->D=1 OR INDIV=1-->D=2
//
// Step 1
ustat1 = dm(PMCTL);
bit clr ustat1 BIT_6|BIT_7; // PLLD=2
bit set ustat1 BIT_6|BIT_9; // DIVEN=1
dm(PMCTL) = ustat1;
// Step 2 (Wait at least 16 CCLK cycles)
lcntr=20, do first_div_delay until lce;
first_div_delay: nop;
// Step 3
ustat1 = dm(PMCTL);
bit clr ustat1 BIT_9; // DIVEN=0
bit set ustat1 BIT_8|BIT_15; // PLLBP=1
dm(PMCTL) = ustat1;
// Step 4 (Wait at least 4096 CCLK cycles)
lcntr=5000, do first_bypass_delay until lce;
first_bypass_delay:nop;
// Step 5
ustat1 = dm(PMCTL);
bit clr ustat1 BIT_15; // PLLBP=0
dm(PMCTL) = ustat1;
// Step 6 (Wait at least 16 CCLK cycles)
lcntr=20, do second_div_delay until lce;
second_div_delay:nop;
// Step 7
ustat1 = dm(PMCTL);
bit clr ustat1 BIT_0|BIT_1|BIT_2|BIT_3|BIT_4|BIT_5|BIT_8; // PLLM=0 & INDIV=0
bit set ustat1 BIT_0|BIT_1|BIT_2|BIT_3|BIT_15; // PLLM=15 & PLLBP=1
dm(PMCTL) = ustat1;
// Step 8 (Wait at least 4096 CCLK cycles)
lcntr=5000, do second_bypass_delay until lce;
second_bypass_delay:nop;
// Step 9
ustat1 = dm(PMCTL);
bit clr ustat1 BIT_15; // PLLBP=0
dm(PMCTL) = ustat1;
// Step 10 (Wait at least 16 CCLK cycles)
lcntr=20, do third_div_delay until lce;
third_div_delay:nop;
// Step 11
ustat1 = dm(PMCTL);
bit clr ustat1 BIT_6|0x1C0000; // PLLM=0 & ?
bit set ustat1 0x00000000|0x00000000|BIT_19; // ? & ? DIVEN=1
dm(PMCTL) = ustat1;
// Step 12 (Wait at least 16 CCLK cycles)
lcntr=20, do forth_div_delay until lce;
forth_div_delay:nop;
InitPLL.end: rts;
