I have been reviewing the DAI section of the ADSP-2156x HRM and I believe I have found a few mistakes.
In the Cross Mode Connections - Shared Clock description (pg 21-9), DAI0_PIN03 & DAI1_PIN03 are referenced. I believe that DAI0_PIN05 & DAI_PIN1_PIN05 have the same functionality. This would be consistent with Table 21-6, but not Table 21-7. I think that Table 21-7 is wrong too in A-Clocks. It should also include DA1 CRS buffer 5. This would be consistent with the register definitions.
In the Cross Mode Connections Shared FS description (pg 21-10), DAI0_PIN04 & DAI1_PIN04 are referenced. I believe that DAI0_PIN06 & DAI_PIN1_PIN06 have the same functionality. This would be consistent with Table 21-6 and Table 21-7.
Fig 21-5 is a clone of Fig 21-6 and is therefore wrong. Pin Buffer Enable should be Low and the External Pin Direction is pointed the wrong direction.
I am assuming the following is true:
- DAI0 & DAI1 are essentially identical in functionality with mirrored cross connections.
- DAI3 & DAI5 have the same cross connection functionality (Clock Source to the other DAI)
- DAI4 & DAI6 have the same cross connection functionality (FS Source to the other DAI)
- To use the PCG from the other DAI, you route this to a Group D Pin Buffer. This Pin Buffer can then be the Source for a Group A or C Destination. This signal will also be available at the corresponding external DAI Pin
I realize that it is very difficult to write a 2000 page mistake free manual and as early adopters, we deal with this. I just want to make sure that my read of the inconsistencies is correct. Is there a manual errata?
Added one more assumption (bullet 4)
[edited by: AlClark at 3:50 PM (GMT 0) on 10 Apr 2020]