Is hardware guidelines provided in EE-387 applicable for DMC of ADSP-21569 processors?

As there is a significant increase in the operating frequency of the Dynamic memory controller, we are in the process of releasing a new Hardware guideline for the DMC Controller. Till that time, Users are advised to use Ezkit schematic and layout for the reference. Below is the list of the good application notes from Micron which users are advised to follow from memory perspective. From the controller perspective, as long as traces are less than 2 inch and standard layout guidelines ( as described in EE-387) are followed users things should be good.

https://www.micron.com/support/~/media/f9b2fb1d2b8c4efc8078247232e25b56.ashx

https://www.micron.com/-/media/client/global/documents/products/technical-note/dram/tn4113_ddr3_point_to_point_design.pdf?la=en

Thanks,
Dhawal