[#5248] "protect on all" timeout in BF518F-EZBRD when icache off

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[#5248] "protect on all" timeout in BF518F-EZBRD when icache off

Submitted By: Vivi Li

Open Date

2009-06-12 07:12:29     Close Date

2010-06-09 23:36:32

Priority:

Low     Assignee:

Mike Frysinger

Category:

N/A     Fixed In Release:

N/A

Found In Release:

2009R1     Status:

Closed

Board:

N/A     Processor:

BF518

Silicon Revision:

    Resolution:

Rejected

Is the bug repeatable?:

N/A     

Summary: "protect on all" timeout in BF518F-EZBRD when icache off

Details:

 

When icache off and dcache on, command "protect on all" timeout in BF518F-EZBRD.

For other three combination of icache and dcache, no such problem.

 

--

bfin> icache off

Instruction Cache is OFF

bfin> dcache on

Data (writethrough) Cache is ON

bfin> protect on all

Protect Flash Bank # 1

.......................................................Flash protect timeout at address 20300000 data 305b00

.Flash protect timeout at address 20310000 data 305b00

.Flash protect timeout at address 20320000 data 305b00

.Flash protect timeout at address 20330000 data 305b00

.Flash protect timeout at address 20340000 data 305b00

.Flash protect timeout at address 20350000 data 305b00

.Flash protect timeout at address 203b0000 data 305b00

.Flash protect timeout at address 203c0000 data 305b00

.Flash protect timeout at address 203d0000 data 305b00

--

 

Follow-ups

 

--- Mike Frysinger                                           2009-06-16 10:40:36

lowering priority:

- not a regression

- it isnt realistic to run w/cache turned off

 

--- Vivi Li                                                  2009-06-25 23:22:38

It also fails when icache off and dcache off in other non-default frequencies,

eg: CCLK 100MHz/SCLK 50MHz, CCLK 400MHz/SCLK 50MHz, CCLK 200MHz/SCLK 100MHz

 

--- Mike Frysinger                                           2010-06-02 22:43:39

seems to work fine regardless of dcache.  fails at same place every time (3rd

bank?) and rather quickly, so i dont think it's a frequency thing.

 

at any rate, i dont think running with icache off in u-boot ever makes sense.

 

--- Mike Frysinger                                           2010-06-04 01:02:17

ASM3 on the BF51x is shared with SPI0 SSEL2.  if you want to test async bank 3,

you need to tweak JP16 and SW3 first.  by default, we want SPI0 SSEL2 because

that's where the SPI flash is which means you cant poke async bank 3 and expect

it to work.

 

also, due to the portmuxing of all SPI0 pins, you really cant use async bank 3

at all.  so dont bother.

 

--- Vivi Li                                                  2010-06-09 23:33:59

So update test script to test banks 0-2.

Close this bug.

 

 

 

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