2011-10-19 19:16:49     128 MB on the BF537 rev 0.3 system

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2011-10-19 19:16:49     128 MB on the BF537 rev 0.3 system

Dimitar Penev (BULGARIA)

Message: 103997   

Hi Guys,

 

I am observing a strange issue I would like to ask about.

 

We have a custom Blackfin BF537 rev 0.3 board with two MT48LC64M8A2P-75 chips in the system.

We are trying to enable the full 128 MB in uboot-2010R1-RC2.

Based on the BF537 datasheet and the excel sheet at http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram&s[]=sdram 

 

I've concluded that I need the following in my board configuration

 

#define CONFIG_MEM_ADD_WDTH     11

#define CONFIG_MEM_SIZE         128

#define CONFIG_EBIU_SDRRC_VAL   0x03A0

#define CONFIG_EBIU_SDGCTL_VAL  0x8091998D

(With these settings SDBCTL registers calculates to 0x0037)

 

We are using LDR version and boot from SPI flash. The SDRAM registers are set from the init code which is called by the CPU boot loader.

With the above register configuration uboot-2010R1-RC2 hangs just after the end of the init code. With debug enabled I see this

ABacCabcdghijDabchijklmnoEadFabcdeGabeHabcI>

 

Booting on our 128MB board is OK if I change

#define CONFIG_MEM_ADD_WDTH     10

#define CONFIG_MEM_SIZE         64

(With these settings SDBCTL registers calculates to 0x0025)

But in this case uboot detects only 64 MB.

 

Some further experiments.

We have a JTAG tool which can load memory testing code.

If I load SDGCTL with 0x0025 (coresponds to MEM_ADD_WDTH =10 and MEM_SIZE=64 ) the memory test goes OK up to the 64MB.

If I load SDGCTL with 0x0037 which in my opinion shoul dbe the proper one (corresponds to MEM_ADD_WDTH =11 and MEM_SIZE =128 ) the memory test reports errors in each odd address.

 

All this makes me think that either we have a hardware issue or I misinterpret the datasheet related with the SDRAM configuration.

Our SDRAM schematics complies with the description in Engineer-to-Engineer Note EE-326

 

Is there someone using two MT48LC64M8A2P-75 chips in BF537-rev0.3 system.

What are the values of the registers (SDBCTL, SDRRC, SDGCTL) which should configure the SDRAM controller properly?

 

Do you guys use the same schematics as it is defined in EE-326 ?

 

Or what can you suggest us to try?

 

Thank you

Dimitar

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2011-10-19 20:18:00     Re: 128 MB on the BF537 rev 0.3 system

Taylor Braun-Jones (UNITED STATES)

Message: 103998   

 

Hi Dimitar - Sorry, I don't have an answer for you, but a question - Would you mind sharing the JTAG memory testing tool you are using? Thanks!

 

Taylor

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2011-10-19 23:58:31     Re: 128 MB on the BF537 rev 0.3 system

Aaron Wu (CHINA)

Message: 104002   

 

memory test reports errors in each odd address, this is interesting, could you share us part of the schematic for your DRAM to BF537 connection?

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2011-10-20 04:39:19     Re: 128 MB on the BF537 rev 0.3 system

Dimitar Penev (BULGARIA)

Message: 104040   

 

Hi Guys,

 

Thank you for the response.

 

Taylor it is a modified version of the memtest code which comes together with ICEbear JTAG tool from www.section5.com

 

Aaron, sure please see the attached picture. On our custom board we have however:

- MT48LC64M8A2 instead of the one shown

- our series termination is 33 Ohm

All the rest is the same. 

 

Note that our jtag memory testing (up to 64MB) is OK If SDGCTL set with 0x0025.

If we set the register with 0x0037 with the JTAG test we can read the even addresses properly and we read

a random values from the odd addresses.

 

So our MT48LC64M8A2 behaves more as MT48LC32M8A2.

Anyone observing similar issue?

 

Best Regards

Dimitar

 

memory.JPG

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2011-10-21 06:03:55     Re: 128 MB on the BF537 rev 0.3 system

Aaron Wu (CHINA)

Message: 104072   

 

Looks like you are confused with SDGCTL and SDBCTL, please double check.

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2011-10-24 12:00:42     Re: 128 MB on the BF537 rev 0.3 system

Dimitar Penev (BULGARIA)

Message: 104135   

 

Hi Aaron,

 

Yes, but probably someone having two

MT48LC64M8 chips on blackfin board can execute in his u-boot

 

uboot> md 0xFFC00A10 3

 

This should help me  a lot.

 

Best Regards

Dimitar

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2011-10-24 22:54:54     Re: 128 MB on the BF537 rev 0.3 system

Aaron Wu (CHINA)

Message: 104138   

 

Hi Dimitar,

 

I mean you are confused SDBCTL with SDGCTL, please check the descriptions of the two registers in the HRM, BIT4 and 5 for SDGCTL is defined as PASR if you set them by mistake you probably get your unexpected result.

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2011-10-25 07:29:38     Re: 128 MB on the BF537 rev 0.3 system

Dimitar Penev (BULGARIA)

Message: 104167   

 

Hi Aaron,

 

Thank you for the response.

 

On my board I get

 

uboot>md ffc00a10 1

ffc00a10: 8011998d

 

At 0xffc00a10 we have SDGCTL and both BIT4 and 5 are not set.

 

If I try

 

pr1>md ffc00a14 1

ffc00a14: 00000025

 

At 0xffc00a14 we have SDBCTL and it is set for 64MB, 10 column address width.

With this settings I get the u-boot starting normally.

 

On my board I have two  MT48LC64M8A2P-75 chips which have column address with 11 and in total 128MB.

If I set SDBCTL  to 0x37 (as I think should be the proper value ) the u-boot fails just after the initcode.

 

What do you guys think sabout all this?

 

Thank you

Dimitar

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2011-10-25 22:56:02     Re: 128 MB on the BF537 rev 0.3 system

Aaron Wu (CHINA)

Message: 104172   

 

Could you move this topic to the new support community?

 

How did you port your code, you may take bf-533 stamp board code and schematic for reference, there we use 128MB DRAM, please port your code by modifying files like include/configs/bf533-stamp.h in u-boot.

 

Actually on BF533 board I get some output like this:

 

bfin> md ffc00a10 1

ffc00a10: 80111109    ....

bfin> md ffc00a14 1

ffc00a14: 00000037    7...

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2011-10-27 11:09:47     Re: 128 MB on the BF537 rev 0.3 system

Dimitar Penev (BULGARIA)

Message: 104215   

 

Hi Aaron, guys,

 

After all we found out that we have an issue with the memory chips itself.

Thank you for the help and very sorry for the disturbance!

 

Best Regards

Dimitar

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