2011-08-09 15:30:34     u-boot-2010.06-2010R1-RC2 bf532 sdram init fails with 32 bit read, 16 bit ok

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2011-08-09 15:30:34     u-boot-2010.06-2010R1-RC2 bf532 sdram init fails with 32 bit read, 16 bit ok

Erik Lidgren (SWEDEN)

Message: 102870   

 

I'm trying to port u-boot-2010.06-2010R1-RC2 to my own hardware with a bf532. I'm getting the SDEASE bit of EBIU_SDSTAT register set on a  32 bit read of the sdram, in the check_hibernation function in initcode.c. So the sdram init fails.

 

if (hibernate_magic[0] == 0xDEADBEEF)

 

After some testing I found that if I added a 16 bit read just after writing to the sdram registers, the sdram inits ok.

 

__builtin_bfin_ssync();

*((volatile uint16_t *)CONFIG_SYS_SDRAM_BASE);

 

So I am uncertain of what the problem could be? I've tried searching and found some sdram init code on the analog EngineerZone that does a 16-bit read of sdram after writing the sdram registers, and then it waits for the SDRS bit to clear before continuing.

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2011-08-09 23:47:28     Re: u-boot-2010.06-2010R1-RC2 bf532 sdram init fails with 32 bit read, 16 bit ok

Sonic Zhang (CHINA)

Message: 102872   

 

We don't see this issue on BF533 and have no bf532 to validate.

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2011-08-10 19:23:09     Re: u-boot-2010.06-2010R1-RC2 bf532 sdram init fails with 32 bit read, 16 bit ok

Erik Lidgren (SWEDEN)

Message: 102887   

 

Hello

 

Thank you for responding.

 

As this is new hardware I'm wondering if this could be a hardware issue. I have tried memory speeds from 50-150MHz, all speeds work if I do a 16-bit read to init, all speeds fail with the original code. I am going to let it run at 150MHz with mtest running for a longer period to see if I can get it to fail.

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2011-08-14 17:01:30     Re: u-boot-2010.06-2010R1-RC2 bf532 sdram init fails with 32 bit read, 16 bit ok

Erik Lidgren (SWEDEN)

Message: 102929   

 

It has been running at 500 MHz core and 166.67MHz system for a few days. I added video support, so it is now also constantly reading the framebuffer in SDRAM in addition to mtest. I will set the frequency back to 400 MHz core and 133.33MHz system from now on.

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