2011-04-21 17:53:15     Using bfin_read_SYSCR() to determine how BF524 was started

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2011-04-21 17:53:15     Using bfin_read_SYSCR() to determine how BF524 was started

Reggy Perrin (UNITED STATES)

Message: 100097   

 

Hi folks,

 

I'm trying to use SYSCR to determine if we are rebooting (either via a s/w reboot in uclinux or a watch-dog timer reset).  Currently, I'm just printing out this code now:

 

unsigned flags = bfin_read_SYSCR();

printf("SYSCR: %x\n",flags);

 

However, I don't see any difference in that register when I boot by powering on from nothing, or from a linux reboot. 

 

I am, however, doing in the following function of u-boot:

 

static __inline__ int abortboot(int bootdelay)

 

My goal was to say "if ( flags & ????)"... and make a decision based on the flags I read. However, I only get "0x0D" from the bfin_read_SYSCR() function.  Am I using this incorrectly?

 

Thanks,

RP

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2011-04-21 18:02:44     Re: Using bfin_read_SYSCR() to determine how BF524 was started

Mike Frysinger (UNITED STATES)

Message: 100098   

 

if you type "reset" at the u-boot prompt, do you see the same thing ?

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2011-04-21 19:45:02     Re: Using bfin_read_SYSCR() to determine how BF524 was started

Reggy Perrin (UNITED STATES)

Message: 100101   

 

Yes

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2011-04-21 20:03:10     Re: Using bfin_read_SYSCR() to determine how BF524 was started

Mike Frysinger (UNITED STATES)

Message: 100103   

 

unfortunately, the BF52[246] have an anomaly where soft reset hangs if SWRST isnt cleared.  so it gets cleared every time you reset.

 

what sirev are you targeting ?  if you build for bf524-0.1+, the anomaly workarounds should be disabled and things start to work.  you can see the code in arch/blackfin/cpu/reset.c in u-boot.

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2011-04-21 20:09:05     Re: Using bfin_read_SYSCR() to determine how BF524 was started

Reggy Perrin (UNITED STATES)

Message: 100104   

 

I have this defined:

 

#define CONFIG_BFIN_CPU             bf524-0.2

 

Would it be possible to save the boot state in reset.c for use later?

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2011-04-21 20:26:10     Re: Using bfin_read_SYSCR() to determine how BF524 was started

Mike Frysinger (UNITED STATES)

Message: 100105   

 

review your reset.c and make sure the if statement in bfin_reset says:

if (ANOMALY_05000353 || ANOMALY_05000386) {

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2011-04-21 20:31:48     Re: Using bfin_read_SYSCR() to determine how BF524 was started

Reggy Perrin (UNITED STATES)

Message: 100106   

 

It does:

 

    if (ANOMALY_05000353 || ANOMALY_05000386) {

        /* Initiate System software reset. */

        bfin_write_SWRST(0x7);

 

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2011-04-21 20:41:57     Re: Using bfin_read_SYSCR() to determine how BF524 was started

Mike Frysinger (UNITED STATES)

Message: 100107   

 

then you can verify in the disassembly that it does:

00000000 <_bfin_reset>:

   0:   24 00           SSYNC;

   2:   91 00           RAISE 0x1;

   4:   ff 2f           JUMP.S 0x2 <_bfin_reset+0x2>;

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2011-04-21 21:56:52     Re: Using bfin_read_SYSCR() to determine how BF524 was started

Reggy Perrin (UNITED STATES)

Message: 100109   

 

I don't think it is.  I executed the following command:

 

bfin-uclinux-gcc  -g  -Os  -Wa,-a,-ad -ffixed-P3 -fomit-frame-pointer -mno-fdpic -ffunction-sections -fdata-sections -mcpu=bf524-0.0 -D__KERNEL__ -Iuboot-tests/u-boot-2010.06-2010R1-RC2/include -fno-builtin -ffreestanding -nostdinc -isystem /opt/toolchain/4.3/bfin-uclinux/bin/../lib/gcc/bfin-uclinux/4.3.5/include -pipe  -DCONFIG_BLACKFIN -Wall -Wstrict-prototypes -fno-stack-protector  -o reset.o reset.c -c

 

(took the command line that was executed for reset.c during normal build and added -Wa,-a,-ad)

 

I don't see it in the results:

 

BFIN GAS               page 1

 

 

   1                  .file "reset.c"

   9                  .Ltext0:

  10                  .section .text.do_reset,"ax",@progbits

  11                  .align 4

  12                  .global _do_reset

  14                  _do_reset:

  15                  .LFB88:

  16                  .file 1 "reset.c"

   1:reset.c       **** /*

   2:reset.c       ****  * reset.c - logic for resetting the cpu

   3:reset.c       ****  *

   4:reset.c       ****  * Copyright (c) 2005-2008 Analog Devices Inc.

   5:reset.c       ****  *

   6:reset.c       ****  * Licensed under the GPL-2 or later.

   7:reset.c       ****  */

   8:reset.c       ****

   9:reset.c       **** #include <common.h>

  10:reset.c       **** #include <command.h>

  11:reset.c       **** #include <asm/blackfin.h>

  12:reset.c       **** #include "cpu.h"

  13:reset.c       ****

  14:reset.c       **** /* A system soft reset makes external memory unusable so force

  15:reset.c       ****  * this function into L1.  We use the compiler ssync here rather

  16:reset.c       ****  * than SSYNC() because it's safe (no interrupts and such) and

  17:reset.c       ****  * we save some L1.  We do not need to force sanity in the SYSCR

  18:reset.c       ****  * register as the BMODE selection bit is cleared by the soft

  19:reset.c       ****  * reset while the Core B bit (on dual core parts) is cleared by

  20:reset.c       ****  * the core reset.

  21:reset.c       ****  */

  22:reset.c       **** __attribute__ ((__l1_text__, __noreturn__))

  23:reset.c       **** static void bfin_reset(void)

  24:reset.c       **** {

  25:reset.c       ****     /* Wait for completion of "system" events such as cache line

  26:reset.c       ****      * line fills so that we avoid infinite stalls later on as

  27:reset.c       ****      * much as possible.  This code is in L1, so it won't trigger

  28:reset.c       ****      * any such event after this point in time.

  29:reset.c       ****      */

  30:reset.c       ****     __builtin_bfin_ssync();

  31:reset.c       ****

  32:reset.c       ****     /* The bootrom checks to see how it was reset and will

  33:reset.c       ****      * automatically perform a software reset for us when

  34:reset.c       ****      * it starts executing after the core reset.

  35:reset.c       ****      */

  36:reset.c       ****     if (ANOMALY_05000353 || ANOMALY_05000386) {

  37:reset.c       ****         /* Initiate System software reset. */

  38:reset.c       ****         bfin_write_SWRST(0x7);

  39:reset.c       ****

  40:reset.c       ****         /* Due to the way reset is handled in the hardware, we need

  41:reset.c       ****          * to delay for 10 SCLKS.  The only reliable way to do this is

  42:reset.c       ****          * to calculate the CCLK/SCLK ratio and multiply 10.  For now,

  43:reset.c       ****          * we'll assume worse case which is a 1:15 ratio.

  44:reset.c       ****          */

  45:reset.c       ****         asm(

  46:reset.c       ****             "LSETUP (1f, 1f) LC0 = %0\n"

  47:reset.c       ****             "1: nop;"

  48:reset.c       ****             :

  49:reset.c       ****             : "a" (15 * 10)

BFIN GAS               page 2

 

 

  50:reset.c       ****             : "LC0", "LB0", "LT0"

  51:reset.c       ****         );

  52:reset.c       ****

  53:reset.c       ****         /* Clear System software reset */

  54:reset.c       ****         bfin_write_SWRST(0);

  55:reset.c       ****

  56:reset.c       ****         /* The BF526 ROM will crash during reset */

  57:reset.c       **** #if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)

  58:reset.c       ****         bfin_read_SWRST();

  59:reset.c       **** #endif

  60:reset.c       ****

  61:reset.c       ****         /* Wait for the SWRST write to complete.  Cannot rely on SSYNC

  62:reset.c       ****          * though as the System state is all reset now.

  63:reset.c       ****          */

  64:reset.c       ****         asm(

  65:reset.c       ****             "LSETUP (1f, 1f) LC1 = %0\n"

  66:reset.c       ****             "1: nop;"

  67:reset.c       ****             :

  68:reset.c       ****             : "a" (15 * 1)

  69:reset.c       ****             : "LC1", "LB1", "LT1"

  70:reset.c       ****         );

  71:reset.c       ****     }

  72:reset.c       ****

  73:reset.c       ****     while (1)

  74:reset.c       ****         /* Issue core reset */

  75:reset.c       ****         asm("raise 1");

  76:reset.c       **** }

  77:reset.c       ****

  78:reset.c       **** /* We need to trampoline ourselves up into L1 since our linker

  79:reset.c       ****  * does not have relaxtion support and will only generate a

  80:reset.c       ****  * PC relative call with a 25 bit immediate.  This is not enough

  81:reset.c       ****  * to get us from the top of SDRAM into L1.

  82:reset.c       ****  */

  83:reset.c       **** __attribute__ ((__noreturn__))

  84:reset.c       **** static inline void bfin_reset_trampoline(void)

  85:reset.c       **** {

  86:reset.c       ****     if (board_reset)

  87:reset.c       ****         board_reset();

  88:reset.c       ****     while (1)

  89:reset.c       ****         asm("jump (%0);" : : "a" (bfin_reset));

  90:reset.c       **** }

  91:reset.c       ****

  92:reset.c       **** __attribute__ ((__noreturn__))

  93:reset.c       **** void bfin_reset_or_hang(void)

  94:reset.c       **** {

  95:reset.c       **** #ifdef CONFIG_PANIC_HANG

  96:reset.c       ****     hang();

  97:reset.c       **** #else

  98:reset.c       ****     bfin_reset_trampoline();

  99:reset.c       **** #endif

100:reset.c       **** }

101:reset.c       ****

102:reset.c       **** int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])

103:reset.c       **** {

  17                  .loc 1 103 0

  18                  .LVL0:

  19                  .LBB4:

BFIN GAS               page 3

 

 

  20                  .LBB6:

  21                  .loc 1 86 0

  22 0000 4AE10000     P2.H =_board_reset

  23                  .LBE6:

  24                  .LBE4:

  25                  .loc 1 103 0

  26 0004 6701         [--SP] =RETS

  27                  .LCFI0:

  28                  .LBB8:

  29                  .LBB5:

  30                  .loc 1 86 0

  31 0006 0AE10000     P2.L =_board_reset

  32                  .LBE5:

  33                  .LBE8:

  34                  .loc 1 103 0

  35 000a A66F         SP +=-12

  36                  .LCFI1:

  37                  .LBB9:

  38                  .LBB7:

  39                  .loc 1 86 0

  40 000c 420C         cc =P2==0

  41 000e 0218         if cc jump .L2

  42                  .loc 1 87 0

  43 0010 6200         call (P2)

  44                  .LVL1:

  45                  .L2:

  46                  .loc 1 89 0

  47 0012 4AE10000     P2.H =_bfin_reset

  48 0016 0AE10000     P2.L =_bfin_reset

  49                  .L4:

  50                 

  51                 

  52 001a 5200         jump (P2)

  53                 

  54                 

  55 001c FF2F         jump.s .L4

  56                  .LBE7:

  57                  .LBE9:

  58                  .LFE88:

  60 001e 0000         .section .l1.text,"ax",@progbits

  61                  .align 4

  63                  _bfin_reset:

  64                  .LFB85:

  65                  .loc 1 24 0

  66                  .loc 1 30 0

  67 0000 2400         ssync

  68                  .loc 1 38 0

  69 0002 49E1C0FF     P1.H =65472

  70 0006 09E10001     P1.L =256

  71 000a 3860         R0 =7(X)

  72                 

  73                 

  74 000c 0897         w[P1] =R0

  75                 

  76                  .loc 1 45 0

  77                 

  78 000e 2AE19600     P2 =150(X)

BFIN GAS               page 4

 

 

  79                 

  80                 

  81 0012 A2E00220     LSETUP (1f,1f)LC0=P2

  82 0016 0000         1:nop

  83                 

  84                  .loc 1 54 0

  85                 

  86 0018 0060         R0 =0(X)

  87                 

  88                 

  89 001a 0897         w[P1] =R0

  90                 

  91                 

  92                  .LBB10:

  93                  .loc 1 58 0

  94                 

  95                 

  96 001c 0895         R0 =w[P1](z)

  97                 

  98                  .LVL2:

  99                 

100                  .LBE10:

101                  .loc 1 64 0

102 001e 7A68         P2 =15(X)

103                 

104                 

105 0020 B2E00220     LSETUP (1f,1f)LC1=P2

106 0024 0000         1:nop

107                 

108                 

109                  .L6:

110                  .loc 1 75 0

111                 

112                 

113 0026 9100         raise 1

114                 

115                 

116 0028 FF2F         jump.s .L6

117                  .LFE85:

119 002a 0000         .section .text.bfin_reset_or_hang,"ax",@progbits

120                  .align 4

121                  .global _bfin_reset_or_hang

123                  _bfin_reset_or_hang:

124                  .LFB87:

125                  .loc 1 94 0

126 0000 6701         [--SP] =RETS

127                  .LCFI2:

128 0002 A66F         SP +=-12

129                  .LCFI3:

130                  .loc 1 96 0

131 0004 FFE3FEFF     call _hang

132                  .LFE87:

134                  .weak _board_reset

195                  .Letext0:

BFIN GAS               page 5

 

 

DEFINED SYMBOLS

                            *ABS*:00000000 reset.c

    {standard input}:14     .text.do_reset:00000000 _do_reset

    {standard input}:63     .l1.text:00000000 _bfin_reset

    {standard input}:123    .text.bfin_reset_or_hang:00000000 _bfin_reset_or_hang

 

UNDEFINED SYMBOLS

_board_reset

_hang

 

 

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2011-04-22 02:47:50     Re: Using bfin_read_SYSCR() to determine how BF524 was started

Mike Frysinger (UNITED STATES)

Message: 100114   

 

in the compile line you posted, i see "mcpu=bf524-0.0".  you must build against 0.1 or newer as i said.

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2011-04-22 09:16:06     Re: Using bfin_read_SYSCR() to determine how BF524 was started

Reggy Perrin (UNITED STATES)

Message: 100130   

 

Thanks, Mike.  Our config.mk was set differently than our .h file (apparently the -mcpu=xxxx comes from the board config.mk).  There was verbage in there about something not being used, so I didn't change it properly.

 

However, that still doesn't fix the problem.  I've rebuilt using the new config.mk, and it definitely uses -mcpu=bf524-0.2.

The assembly shows:

 

  47 0012 4AE10000  P2.H =_bfin_reset

  48 0016 0AE10000  P2.L =_bfin_reset

  49               .L4:

  50             

  51             

  52 001a 5200      jump (P2)

  53             

  54             

  55 001c FF2F      jump.s .L4

  56               .LBE7:

  57               .LBE9:

  58               .LFE88:

  60 001e 0000      .section .l1.text,"ax",@progbits

  61               .align 4

  63               _bfin_reset:

  64               .LFB85:

  65               .loc 1 24 0

  66               .loc 1 30 0

  67 0000 2400      ssync

  68               .L6:

  69               .loc 1 75 0

  70             

  71             

  72 0002 9100      raise 1

  73             

  74             

  75 0004 FF2F      jump.s .L6

  76               .LFE85:

  78 0006 0000      .section .text.bfin_reset_or_hang,"ax",@progbits

  79               .align 4

 

I'm still seeing the same output from the bfin_read_SYSCR() function:  0x0d.

 

Can you think of anything else?

 

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2011-04-22 17:21:44     Re: Using bfin_read_SYSCR() to determine how BF524 was started

Mike Frysinger (UNITED STATES)

Message: 100132   

 

that should fix u-boot's "reset" only.  is that what you're testing ?  or are you throwing Linux into the mix ?

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2011-04-22 17:43:40     Re: Using bfin_read_SYSCR() to determine how BF524 was started

Reggy Perrin (UNITED STATES)

Message: 100133   

 

No, I need to detect if the startup is due to pressing our POWER button.  If so, we want them to press-hold POWER for 2s before we start. 

 

We are sensing this using the GPIO of the POWER button.  This is currently working, but we can briefly tap the POWER button and fool the system.  It's almost as if you can tap/release the POWER button before u-boot's main_loop() starts (that's where my code is).  I essentially wrapped the boot delay with logic to abort and shut down under certain conditions.

 

That led me to try and detect the initial state of the system using the SYSCR register.  So, rather than saying:

 

inital = !bfin_gpio_get_value(GPIO_PF6);

 

I was trying to do:

 

initial = bfin_read_SYSCR() & ______;    // (I hadn't worked out the bit flags yet)

 

So, determine from SYSCR that this was a power-on-reset boot, not a reboot.  However, doing a:

 

printf("initial=%x\n",bfin_read_SYSCR());

 

always shows "0x0D" in main_loop(), regardless of if I power up using the POWER button, or reset from the bfin> u-boot prompt, or reboot from the uclinux prompt.

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2011-04-25 13:47:47     Re: Using bfin_read_SYSCR() to determine how BF524 was started

Reggy Perrin (UNITED STATES)

Message: 100148   

 

Mike, any thoughts?

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2011-04-28 15:27:07     Re: Using bfin_read_SYSCR() to determine how BF524 was started

Mike Frysinger (UNITED STATES)

Message: 100269   

 

it seems the hardware does not match the documentation and simply doing "RAISE 1" does not result in a proper software reset.  you can probably use this patch with the 2010R1 to make things work as you want:

 

--- a/arch/blackfin/cpu/reset.c

+++ b/arch/blackfin/cpu/reset.c

@@ -9,6 +9,7 @@

#include <common.h>

#include <command.h>

#include <asm/blackfin.h>

+#include <asm/mach-common/bits/bootrom.h>

#include "cpu.h"

 

/* A system soft reset makes external memory unusable so force

@@ -68,7 +69,8 @@ static void bfin_reset(void)

            : "a" (15 * 1)

            : "LC1", "LB1", "LT1"

        );

-   }

+   } else

+       bfrom_SoftReset(L1_SRAM_SCRATCH_END - 20);

 

    while (1)

        /* Issue core reset */

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