2011-02-22 10:27:27     Frequency scaling

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2011-02-22 10:27:27     Frequency scaling

Thomas Z (SWEDEN)

Message: 98335   

 

Hi. I'm trying to scale the frequency of our bf561-0.5 from 600 MHz down to 495 MHz due to that the bf561 has some anomalies listed that applies when running it at 600 MHz. And from what I understand I should only need to change the clock settings in the board configuration file. However, u-boot won't boot now. We did run the CPU at 495 MHz before we switched to u-boot/uClinux using the same scaling parameters. What do I have to do to make it work in u-boot?

 

The clock settings look like this:

 

/*

* Clock Settings

*    CCLK = (CLKIN * VCO_MULT) / CCLK_DIV

*    SCLK = (CLKIN * VCO_MULT) / SCLK_DIV

*/

 

/* CONFIG_CLKIN_HZ is any value in Hz                    */

#define CONFIG_CLKIN_HZ            30000000

 

/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN        */

/*                                                                                        1 = CLKIN / 2        */

#define CONFIG_CLKIN_HALF        0

 

/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass    */

/*                                                                                               1 = bypass PLL    */

#define CONFIG_PLL_BYPASS        0

 

/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL        */

/* Values can range from 0-63 (where 0 means 64)            */

#define CONFIG_VCO_MULT            33

 

/* CCLK_DIV controls the core clock divider                */

/* Values can be 1, 2, 4, or 8 ONLY                    */

#define CONFIG_CCLK_DIV            2

 

/* SCLK_DIV controls the system clock divider                */

/* Values can range from 1-15                        */

#define CONFIG_SCLK_DIV            8

 

 

 

Best regards

 

//Thomas

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2011-02-22 10:37:24     Frequency scaling

Wojtek Skulski (UNITED STATES)

Message: 98336    Thomas:

 

I am ruuning BF561-0.5 at 600 MHz and have not seen any problems yet. But

I got worried by what you said about anomalies. Can you please point me

to the list of these?

 

Thank you -- Wojtek

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2011-02-22 10:54:28     Re: Frequency scaling

Thomas Z (SWEDEN)

Message: 98337   

 

http://www.analog.com/static/imported-files/ic_anom/BF561_icanomlyRevQ_110708.pdf

 

Most of them only applies to the 0.3 revision but there are a few for 0.5 as well. Since you haven't had any problems you probably shouldnt worry, unless you're still developing =), but I guess it's good to know about it anyway. In our case we had some DMA issues that was described in this list and it could be solved by running the CPU at 495 MHz.

 

//Thomas

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2011-02-22 12:36:06     Re: Frequency scaling

Mike Frysinger (UNITED STATES)

Message: 98340   

 

what anomalies exactly are you worried about ?  we do all of our testing/verification at 600MHz.  the only reason we default SCLK to 100MHz is because of poorly designed addon cards.

 

when you change clock timings, you might also need to update your SDRAM timings.

 

also, you dont need to flash u-boot in order to test out the new settings.  simply load it into external memory and do "go" on it ... u-boot will take care of reprogramming clocks automatically.

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2011-02-22 12:37:33     Re: Frequency scaling

Wojtek Skulski (UNITED STATES)

Message: 98342    Thomas:

 

I am still developing. Thank you for the info. -- Wojtek

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2011-02-23 10:11:16     Re: Frequency scaling

Thomas Z (SWEDEN)

Message: 98378   

 

Mike:

 

I'm still having problems getting it to work. I think I'm close to calculating RDIV correctly but for some reason it doesn't work. I'm pretty certain about f_SCLK, t_REF and NRA but i'm not that certain about  t_RP and t_RAS. Any advice on how to set these two? Previously when we used this clock setting t_RAS was 6 and t_RP 3. But that doens't work for me.

 

the working 600/100 MHz version has these settings: (t_REF = 64 ms, NRA = 8192)

 

#define CONFIG_EBIU_SDRRC_VAL      0x306

#define CONFIG_EBIU_SDGCTL_VAL    0x91114d

 

Are there any other settings in EBIU_SDGCTL that I need to change from the working 600/100 MHz version?

 

 

 

Regarding the anomaly

 

It's number 19 on the list. Do we need to worry about this under uClinux?

 

19. 05000182 - Internal Memory DMA Does Not Operate at Full Speed

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2011-02-23 12:25:26     Re: Frequency scaling

Mike Frysinger (UNITED STATES)

Message: 98379   

 

please use the spreadsheet:

http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram#calculating_sdram_settings

 

you only need to worry about anomaly 182 if you plan on using core b.  the kernel itself takes care of checking for this at runtime:

        if (get_cclk() > 500000000) {

            printk(KERN_WARNING

                   "Request IMDMA failed due to ANOMALY 05000182\n");

            return -EFAULT;

        }

 

so if you dont hit that message, you wont have a problem.

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2011-02-24 04:57:42     Re: Frequency scaling

Thomas Z (SWEDEN)

Message: 98394   

 

Thanks Mike. Good and bad news.

 

The bad news is that I got the same values from the spreadsheet as I had got from my initial calculations = still doesn't work at 495/123.75 MHz.

 

The good news is that it seems as if we won't be bothered by that anomaly under uClinux, i.e we can run the core at 600 MHz.

 

We still want the SCLK up though so I tried to divide 600 MHz with 5 to get 120 MHz which probably will be enough for our connected harware. I used the same calculations as before to get RDIV, and it worked instantly =) Don't know what was wrong with the other setting though.

 

Anyway, thanks again for your support Mike.

 

Best regards

 

//Thomas

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