2010-11-23 22:14:47     Cannot change CCLK/SCLK

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2010-11-23 22:14:47     Cannot change CCLK/SCLK

Wojtek Skulski (UNITED STATES)

Message: 96148   




Somehow I cannot change the CCLK/SCLK in uBoot. N matter what I am doing, my board always is running CCLK=200 MHz, and SCLK=100MHz. Is there something magic about these settings? Are they hardcoded somewhere?


U-Boot 2010.06-svn2356 (ADI-2010R1-pre) (Nov 23 2010 - 21:18:31)


CPU:   ADSP bf561-0.5 (Detected Rev: 0.5) (spi flash boot)

Board: BlackVME

Clock: VCO: 200 MHz, Core: 200 MHz, System: 100 MHz


I just changed my board file blackvme.h as follows, recompiled and reloaded uBoot, and it still is running 200/100, even though the CONFIG settings should be 600 MHz/120 MHz. But no matter how I am changing these numbers, the change has no effect.


#define CONFIG_CLKIN_HZ         25000000

#define CONFIG_CLKIN_HALF       0

#define CONFIG_PLL_BYPASS       0

#define CONFIG_VCO_MULT         24

#define CONFIG_CCLK_DIV         1

#define CONFIG_SCLK_DIV         5



I am attaching the entire board config file for reference.






2010-11-24 01:31:43     Re: Cannot change CCLK/SCLK

Mike Frysinger (UNITED STATES)

Message: 96152   


might want to make sure initcode is being rebuilt with `make clean`




2010-11-24 02:36:27     Re: Cannot change CCLK/SCLK

Aaron Wu (CHINA)

Message: 96153   


I tried on a bf537 board, the change as you mentioned works. So you may try to make clean it and try again as Mike suggested. Also note that if you want to change the SCLK, you may also want to check the periherals clocks that derives from it such as the baudrate for the UART to make sure they will work properly.




2010-11-24 02:43:10     Re: Cannot change CCLK/SCLK

Mike Frysinger (UNITED STATES)

Message: 96154   


all the Blackfin drivers should take care of the SCLK divisions automatically




2010-11-24 10:29:49     Re: Cannot change CCLK/SCLK

Wojtek Skulski (UNITED STATES)

Message: 96177   




thank you for the hint. I made clean, rebuild the uBott, and it now starts as expected with CCLK/SCLK = 600/120. The UART boot console is working as before, just like you predicted. The UART baud rate did not change. I was afraid that the chip will get hot after incresing the CCLK, but it is barely warm.


One thing that concerns me is the BogoMIPS report printed by the kernel. It says Calibrating delay loop... 1187.84 BogoMIPS (lpj=593920). I expected twice as much because of two cores. The boot messages reproduced on your website all report 2*CCLK as BogoMIPS rating for single-core Blackfins, but BF561 being dual-core should report twice as many BogoMIPS. At least I thought so. Any comments what is the meaning of BogoMIPS in this case?




2010-11-24 16:09:52     Re: Cannot change CCLK/SCLK

Mike Frysinger (UNITED STATES)

Message: 96182   


BogoMIPS has nothing to do with core count