2010-09-28 09:13:11     Porting of U-bootloader

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2010-09-28 09:13:11     Porting of U-bootloader

Shyam sundar (INDIA)

Message: 93905   

 

Hello world,

 

I am using a customised board having BF537 as the processor.

 

I am trying to port the uboot loader as per the documentation.At the end of the post is the config file I am using.

 

I am trying to boot from a Winbond SPI flash. I do get the following message in the console

 

QST>

 

then after 40 seconds

 

ABCDEGHIJKLMNOPQST>

 

I have enabled the early serial debugging option because of which I am able to see above prints in the console.

 

The CLKIN is 24.567 MHz and the SDRAM size is 32MB.

 

I have tested the SDRAM in VDSP environment using the config as mentioned in the config file.

 

I did burn the ldr file created using an emulator in the VDSP platform.

 

While executing the initcode, why only QST> is displayed on console and not the other characters,even after I have enabled the early serial debug? If I view the generated ldr files,the format looks to be ok!

 

Do I need to change any other settings other than which I have specified below?

 

Sorry for reposting this! I had posted this problem in the uclinux forum!

 

 

 

/*

* U-boot - Configuration file for BF537 VOIP board

*/

 

#ifndef __CONFIG_BF537_VOIP_H__

#define __CONFIG_BF537_VOIP_H__

 

#include <asm/blackfin-config-pre.h>

 

 

/*

* Processor Settings

*/

#define CONFIG_BFIN_CPU             bf537-0.3

#define CONFIG_BFIN_BOOT_MODE    BFIN_BOOT_SPI_MASTER

 

 

#define CONFIG_CLKIN_HZ            24576000

#define CONFIG_CLKIN_HALF        0

#define CONFIG_PLL_BYPASS        0

#define CONFIG_VCO_MULT            20

#define CONFIG_CCLK_DIV            1

#define CONFIG_SCLK_DIV            4

 

 

/*

* Memory Settings

*/

 

#define CONFIG_MEM_ADD_WDTH    9

#define CONFIG_MEM_SIZE        32

 

#define CONFIG_EBIU_SDRRC_VAL    0x181

#define CONFIG_EBIU_SDGCTL_VAL    0x818910CD

 

#define CONFIG_EBIU_AMGCTL_VAL    0xFF

#define CONFIG_EBIU_AMBCTL0_VAL    0x7BB07BB0

#define CONFIG_EBIU_AMBCTL1_VAL    0xFFC27BB0

 

 

#define CFG_MONITOR_LEN        (512 * 1024)

#define CFG_MALLOC_LEN        (384 * 1024)

 

 

/*

* Network Settings

*/

#ifndef __ADSPBF534__

#define ADI_CMDS_NETWORK    1

#define CONFIG_BFIN_MAC

#define CONFIG_NETCONSOLE    1

#define CONFIG_NET_MULTI    1

#endif

#define CONFIG_HOSTNAME        bf537-VOIP

/* Uncomment next line to use fixed MAC address */

/* #define CONFIG_ETHADDR    02:80:ad:20:31:e8 */

 

 

/*

* Flash Settings

*/

#define CFG_FLASH_BASE        0x20000000

#define CFG_FLASH_CFI        /* The flash is CFI compatible */

#define CONFIG_FLASH_CFI_DRIVER    /* Use common CFI driver */

#define CFG_FLASH_PROTECTION

#define CFG_MAX_FLASH_BANKS    1

#define CFG_MAX_FLASH_SECT    256    /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */

 

#define CONFIG_BFIN_SPI

#define CONFIG_ENV_SPI_MAX_HZ   30000000

#define CONFIG_SF_DEFAULT_HZ    30000000

#define CONFIG_SPI_FLASH

#define CONFIG_SPI_FLASH_WINBOND

 

#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)

#define CONFIG_ENV_IS_IN_SPI_FLASH

#define CONFIG_ENV_OFFSET    0x10000

#define CONFIG_ENV_SIZE        0x2000

#define CONFIG_ENV_SECT_SIZE    0x10000

#else

#define    CONFIG_ENV_IS_IN_FLASH

#define CONFIG_ENV_OFFSET    0x4000

#define CONFIG_ENV_ADDR        (CFG_FLASH_BASE + CONFIG_ENV_OFFSET)

#define CONFIG_ENV_SIZE        0x2000

#define    CONFIG_ENV_SECT_SIZE    0x2000    /* Total Size of Environment Sector */

#endif

#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)

#define ENV_IS_EMBEDDED

#else

#define ENV_IS_EMBEDDED_CUSTOM

#endif

 

/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider        */

/* Values can range from 2-65535                    */

/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)                */

#define CONFIG_SPI

#define CONFIG_SPI_BAUD            2

//#define CFG_I2C_FRAM

 

 

/*

* I2C Settings

*/

#define CONFIG_BFIN_TWI_I2C    1

#define CONFIG_HARD_I2C        1

#define CFG_I2C_SPEED        50000

#define CFG_I2C_SLAVE        0

 

 

/*

* SPI_MMC Settings

*/

#define CONFIG_MMC

#define CONFIG_BFIN_SPI_MMC

 

 

/*

* NAND Settings

*/

/* #define CONFIG_BF537_NAND */

#ifdef CONFIG_BF537_NAND

# define CONFIG_CMD_NAND

#endif

 

#define CFG_NAND_ADDR        0x20212000

#define CFG_NAND_BASE        CFG_NAND_ADDR

#define CFG_MAX_NAND_DEVICE    1

#define SECTORSIZE        512

#define ADDR_COLUMN        1

#define ADDR_PAGE        2

#define ADDR_COLUMN_PAGE    3

#define NAND_ChipID_UNKNOWN    0x00

#define NAND_MAX_FLOORS        1

#define NAND_MAX_CHIPS        1

#define BFIN_NAND_READY        PF3

 

#define NAND_WAIT_READY(nand) \

    do { \

        int timeout = 0; \

        while (!(*pPORTFIO & PF3)) \

            if (timeout++ > 100000) \

                break; \

    } while (0)

 

#define BFIN_NAND_CLE        (1<<2)    /* A2 -> Command Enable */

#define BFIN_NAND_ALE        (1<<1)    /* A1 -> Address Enable */

 

#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_CLE) = (__u8)(d); } while(0)

#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_ALE) = (__u8)(d); } while(0)

#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)

#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))

 

 

/*

* CF-CARD IDE-HDD Support

*/

/* #define CONFIG_BFIN_TRUE_IDE */    /* Add CF flash card support */

/* #define CONFIG_BFIN_CF_IDE */    /* Add CF flash card support */

/* #define CONFIG_BFIN_HDD_IDE */    /* Add IDE Disk Drive (HDD) support */

 

#if defined(CONFIG_BFIN_CF_IDE) || defined(CONFIG_BFIN_HDD_IDE) || defined(CONFIG_BFIN_TRUE_IDE)

# define CONFIG_BFIN_IDE    1

# define CONFIG_CMD_IDE

#endif

 

#if defined(CONFIG_BFIN_IDE)

 

#define CONFIG_DOS_PARTITION    1

/*

* IDE/ATA stuff

*/

#undef  CONFIG_IDE_8xx_DIRECT    /* no pcmcia interface required */

#undef  CONFIG_IDE_LED        /* no led for ide supported */

#undef  CONFIG_IDE_RESET    /* no reset for ide supported */

 

#define CFG_IDE_MAXBUS        1    /* max. 1 IDE busses */

#define CFG_IDE_MAXDEVICE    (CFG_IDE_MAXBUS*1)    /* max. 1 drives per IDE bus */

 

#undef  CONFIG_EBIU_AMBCTL1_VAL

#define CONFIG_EBIU_AMBCTL1_VAL        0xFFC3FFC3

 

#define CONFIG_CF_ATASEL_DIS    0x20311800

#define CONFIG_CF_ATASEL_ENA    0x20311802

 

#if defined(CONFIG_BFIN_TRUE_IDE)

/*

* Note that these settings aren't for the most part used in include/ata.h

* when all of the ATA registers are setup

*/

#define CFG_ATA_BASE_ADDR    0x2031C000

#define CFG_ATA_IDE0_OFFSET    0x0000

#define CFG_ATA_DATA_OFFSET    0x0020    /* Offset for data I/O */

#define CFG_ATA_REG_OFFSET    0x0020    /* Offset for normal register accesses */

#define CFG_ATA_ALT_OFFSET    0x001C    /* Offset for alternate registers */

#define CFG_ATA_STRIDE        2    /* CF.A0 --> Blackfin.Ax */

#endif                /* CONFIG_BFIN_TRUE_IDE */

 

#if defined(CONFIG_BFIN_CF_IDE)    /* USE CompactFlash Storage Card in the common memory space */

#define CFG_ATA_BASE_ADDR    0x20211800

#define CFG_ATA_IDE0_OFFSET    0x0000

#define CFG_ATA_DATA_OFFSET    0x0000    /* Offset for data I/O */

#define CFG_ATA_REG_OFFSET    0x0000    /* Offset for normal register accesses */

#define CFG_ATA_ALT_OFFSET    0x000E    /* Offset for alternate registers */

#define CFG_ATA_STRIDE        1    /* CF.A0 --> Blackfin.Ax */

#endif                /* CONFIG_BFIN_CF_IDE */

 

#if defined(CONFIG_BFIN_HDD_IDE)    /* USE TRUE IDE */

#define CFG_ATA_BASE_ADDR    0x20314000

#define CFG_ATA_IDE0_OFFSET    0x0000

#define CFG_ATA_DATA_OFFSET    0x0020    /* Offset for data I/O */

#define CFG_ATA_REG_OFFSET    0x0020    /* Offset for normal register accesses */

#define CFG_ATA_ALT_OFFSET    0x001C    /* Offset for alternate registers */

#define CFG_ATA_STRIDE        2    /* CF.A0 --> Blackfin.A1 */

 

#undef  CONFIG_SCLK_DIV

#define CONFIG_SCLK_DIV        8

#endif                /* CONFIG_BFIN_HDD_IDE */

 

#endif                /*CONFIG_BFIN_IDE */

 

 

/*

* Misc Settings

*/

#define CONFIG_MISC_INIT_R

#define CONFIG_RTC_BFIN

#define CONFIG_UART_CONSOLE    0

 

/* #define CONFIG_BF537_VOIP_LEDCMD    1 */

 

/* Define if want to do post memory test */

#undef CONFIG_POST

#ifdef CONFIG_POST

#define FLASH_START_POST_BLOCK    11    /* Should > = 11 */

#define FLASH_END_POST_BLOCK    71    /* Should < = 71 */

#endif

 

 

/*

* Pull in common ADI header for remaining command/environment setup

*/

#include <configs/bfin_adi_common.h>

 

#include <asm/blackfin-config-post.h>

 

#endif

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2010-09-28 11:08:17     Re: Porting of U-bootloader

Mike Frysinger (UNITED STATES)

Message: 93912   

 

i already told you: the only thing being executed is your initcode.  not seeing the earlier chars isnt a big deal as long as you get to ">".  after that, you must check your SDRAM and make sure the u-boot.ldr was loaded up into external memory at the right place.

 

using VDSP to debug isnt really supported.  it reprograms MMRs on the fly by default whenever you connect.  this is why you should be using the GNU toolchain to do testing.

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2010-09-28 11:59:10     Re: Porting of U-bootloader

Shyam sundar (INDIA)

Message: 93919   

 

Thanks Mike for bearing with me !!

 

If i am right,at the end of the initcode routine(just before the exit), the SDRAM address(0x01F80000) is specified.

 

In the ldr file I do see that  the target address is 0x01F80000.

 

So this confirms that the bootloader generated is fine. I do agree that there is problem with SDRAM.

 

Can you please tell me, where does this loading routine from the SPI flash to external memory (SDRAM) happens? Does the bootrom takes up this issue?

 

Also can you please tell me how can I use the GNU toolchain to test outthe functionality of the SDRAM?

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2010-09-28 12:06:13     Re: Porting of U-bootloader

Mike Frysinger (UNITED STATES)

Message: 93920   

 

please read the documentation:

https://docs.blackfin.uclinux.org/doku.php?id=bootloaders

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2010-09-28 15:27:05     Re: Porting of U-bootloader

Shyam sundar (INDIA)

Message: 93931   

 

Thanks Mike ! I was going through the bootrom source code and was able to  understand the flow of booting.

 

Is there any test I can perform to check the functionality of the SDRAM ? Or the only way is to experiment with the peripheral clock and the values of the SDRAM control registers as per the BfSdcCalculation_Release.xls file? Please let me know if there is any document which i can read upon !!

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2010-09-28 16:36:51     Re: Porting of U-bootloader

Mike Frysinger (UNITED STATES)

Message: 93935   

 

you could try slowing down the timings.  otherwise, once again, you need to compare the contents of external memory to that of u-boot on your disk to make sure they match byte for byte.

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2010-10-04 08:38:17     Re: Porting of U-bootloader

Shyam sundar (INDIA)

Message: 94167   

 

Thanks Mike !!

 

I have connected a 8MB SPI flash to the BF537 stamp board. I am not able to download the kernel image using the command  tftpboot 0x1000000 vmlinux

 

I have set the serverip and the gatewayip properly!!

 

This is what my u-boot loader output looks like!!

 

Can i know whether i am missing something?

 

ABCDEGHIJKLMNOPQST>

Early:start.S: Init Registers

Early:start.S: Find ourselves

Early:start.S: Lower to 15

Early: Board init flash

 

 

U-Boot 2008.10-svn2396 (ADI-2009R1.1-rc1) (Oct  4 2010 - 17:43:00)

 

CPU:   ADSP bf537-0.3 (Detected Rev: 0.3) (spi flash boot)

Board: ADI BF537 stamp board

       Support: http://blackfin.uclinux.org/

Clock: VCO: 500 MHz, Core: 500 MHz, System: 125 MHz

RAM:   64 MB

Flash:  4 MB

SF: Got idcode f7 80 03

SF: Unsupported manufacturer F7

*** Warning - bad CRC, using default environment

 

In:    serial

Out:   serial

Err:   serial

Net:   Blackfin EMAC

MAC:   00:E0:22:FE:61:73

Hit any key to stop autoboot:  0

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2010-10-06 02:21:40     Re: Porting of U-bootloader

Shyam sundar (INDIA)

Message: 94211   

 

Ooops,there was problem with the tftp server because of which i was not able to dowland the kernal application!!!

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2010-10-08 00:45:58     Re: Porting of U-bootloader

Shyam sundar (INDIA)

Message: 94321   

 

SDRAM problem solved !! I was using 32MB 16 bit SDRAM!! Setting the peripheral clock to 120 MHz and using the control settings as per the BfSdcCalculation_Release.xls solved the problem !! Thanks Mike for the support !

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