2010-09-22 06:20:05     uboot loader not working

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2010-09-22 06:20:05     uboot loader not working

Shyam sundar (INDIA)

Message: 93738   

 

Hello world,

 

I have a custom board which has a BF537 processor

 

I had downloaded the source files for making a u-boot loader by using the following commands

 

svn checkout svn://blackfin.uclinux.org/uclinux-dist//branches/2009R1

 

svn checkout svn://blackfin.uclinux.org/u-boot//branches/2009R1

 

svn checkout svn://blackfin.uclinux.org/toolchain//branches/toolchain_09r1_branch

 

svn checkout svn://blackfin.uclinux.org/linux-kernel//branches/2009R1

 

http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:porting&s[]=config&s[]=bfin&s[]=boot&s[]=mode#porting_u-boot_to_your_board

 

As per the above link,I modified necessary files.

 

I had just copied u-boot/u-boot-2008.10/board/bf537-stamp directory as u-boot/u-boot-2008.10/board/bf537-VOIP directory and made the necessary file renames.

 

I gave the command make bf537-VOIP_config followed by make bf537-VOIP.

 

I used the file u-boot.ldr generated in the path u-boot/u-boot-2008.10 to program the flash using an emulator.

 

I was not able to see nothing on the hyperterminal.

 

The testing of the UART 0 interface was done and it was ok.

 

Why am i not able to see anything on the hyperterminal??

 

This is how my u-boot/u-boot-2008.10/include/configs/bf537-VOIP.h files looks like.

 

The file is almost same as thebf537-stamp.h file except that I am using 32MB SDRAM and 8MB SPI FLASH (W25X64BV).

 

/*

* U-boot - Configuration file for BF537 VOIP board

*/

 

#ifndef __CONFIG_BF537_VOIP_H__

#define __CONFIG_BF537_VOIP_H__

 

#include <asm/blackfin-config-pre.h>

 

 

/*

* Processor Settings

*/

#define CONFIG_BFIN_CPU             bf537-0.3

#define CONFIG_BFIN_BOOT_MODE    BFIN_BOOT_SPI_MASTER

 

 

/*

* Clock Settings

*    CCLK = (CLKIN * VCO_MULT) / CCLK_DIV

*    SCLK = (CLKIN * VCO_MULT) / SCLK_DIV

*/

/* CONFIG_CLKIN_HZ is any value in Hz                    */

#define CONFIG_CLKIN_HZ            25000000

/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN        */

/*                                                1 = CLKIN / 2        */

#define CONFIG_CLKIN_HALF        0

/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass    */

/*                                                1 = bypass PLL    */

#define CONFIG_PLL_BYPASS        0

/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL        */

/* Values can range from 0-63 (where 0 means 64)            */

#define CONFIG_VCO_MULT            20

/* CCLK_DIV controls the core clock divider                */

/* Values can be 1, 2, 4, or 8 ONLY                    */

#define CONFIG_CCLK_DIV            1

/* SCLK_DIV controls the system clock divider                */

/* Values can range from 1-15                        */

#define CONFIG_SCLK_DIV            4

 

 

#define NEW_SDRAM_CONFIG

 

/*

* Memory Settings

*/

#ifdef OLD_SDRAM_CONFIG

 

#define CONFIG_MEM_ADD_WDTH    10

#define CONFIG_MEM_SIZE        64

 

#define CONFIG_EBIU_SDRRC_VAL    0x306

#define CONFIG_EBIU_SDGCTL_VAL    0x91114d

 

#define CONFIG_EBIU_AMGCTL_VAL    0xFF

#define CONFIG_EBIU_AMBCTL0_VAL    0x7BB07BB0

#define CONFIG_EBIU_AMBCTL1_VAL    0xFFC27BB0

 

#endif

 

 

#ifdef NEW_SDRAM_CONFIG

 

#define CONFIG_MEM_ADD_WDTH    9

#define CONFIG_MEM_SIZE        32

 

#define CONFIG_EBIU_SDRRC_VAL    0x181

#define CONFIG_EBIU_SDGCTL_VAL    0x818910dd

 

#define CONFIG_EBIU_AMGCTL_VAL    0xFF

#define CONFIG_EBIU_AMBCTL0_VAL    0x7BB07BB0

#define CONFIG_EBIU_AMBCTL1_VAL    0xFFC27BB0

 

#endif

 

 

#define CFG_MONITOR_LEN        (512 * 1024)

#define CFG_MALLOC_LEN        (384 * 1024)

 

 

/*

* Network Settings

*/

#ifndef __ADSPBF534__

#define ADI_CMDS_NETWORK    1

#define CONFIG_BFIN_MAC

#define CONFIG_NETCONSOLE    1

#define CONFIG_NET_MULTI    1

#endif

#define CONFIG_HOSTNAME        bf537-VOIP

/* Uncomment next line to use fixed MAC address */

/* #define CONFIG_ETHADDR    02:80:ad:20:31:e8 */

 

 

/*

* Flash Settings

*/

#define CFG_FLASH_BASE        0x20000000

#define CFG_FLASH_CFI        /* The flash is CFI compatible */

#define CONFIG_FLASH_CFI_DRIVER    /* Use common CFI driver */

#define CFG_FLASH_PROTECTION

#define CFG_MAX_FLASH_BANKS    1

#define CFG_MAX_FLASH_SECT    256    /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */

 

#define CONFIG_BFIN_SPI

#define CONFIG_ENV_SPI_MAX_HZ   30000000

#define CONFIG_SF_DEFAULT_HZ    30000000

#define CONFIG_SPI_FLASH

//#define CONFIG_SPI_FLASH_STMICRO

#define CONFIG_SPI_FLASH_WINBOND

 

#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)

#define CONFIG_ENV_IS_IN_SPI_FLASH

#define CONFIG_ENV_OFFSET    0x10000

#define CONFIG_ENV_SIZE        0x2000

#define CONFIG_ENV_SECT_SIZE    0x10000

#else

#define    CONFIG_ENV_IS_IN_FLASH

#define CONFIG_ENV_OFFSET    0x4000

#define CONFIG_ENV_ADDR        (CFG_FLASH_BASE + CONFIG_ENV_OFFSET)

#define CONFIG_ENV_SIZE        0x2000

#define    CONFIG_ENV_SECT_SIZE    0x2000    /* Total Size of Environment Sector */

#endif

#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)

#define ENV_IS_EMBEDDED

#else

#define ENV_IS_EMBEDDED_CUSTOM

#endif

 

/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider        */

/* Values can range from 2-65535                    */

/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)                */

/*#define CONFIG_SPI

#define CONFIG_SPI_BAUD            2

#define CFG_I2C_FRAM

*/

 

/*

* I2C Settings

*/

#define CONFIG_BFIN_TWI_I2C    1

#define CONFIG_HARD_I2C        1

#define CFG_I2C_SPEED        50000

#define CFG_I2C_SLAVE        0

 

 

/*

* SPI_MMC Settings

*/

#define CONFIG_MMC

#define CONFIG_BFIN_SPI_MMC

 

 

/*

* NAND Settings

*/

/* #define CONFIG_BF537_NAND */

#ifdef CONFIG_BF537_NAND

# define CONFIG_CMD_NAND

#endif

 

#define CFG_NAND_ADDR        0x20212000

#define CFG_NAND_BASE        CFG_NAND_ADDR

#define CFG_MAX_NAND_DEVICE    1

#define SECTORSIZE        512

#define ADDR_COLUMN        1

#define ADDR_PAGE        2

#define ADDR_COLUMN_PAGE    3

#define NAND_ChipID_UNKNOWN    0x00

#define NAND_MAX_FLOORS        1

#define NAND_MAX_CHIPS        1

#define BFIN_NAND_READY        PF3

 

#define NAND_WAIT_READY(nand) \

    do { \

        int timeout = 0; \

        while (!(*pPORTFIO & PF3)) \

            if (timeout++ > 100000) \

                break; \

    } while (0)

 

#define BFIN_NAND_CLE        (1<<2)    /* A2 -> Command Enable */

#define BFIN_NAND_ALE        (1<<1)    /* A1 -> Address Enable */

 

#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_CLE) = (__u8)(d); } while(0)

#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_ALE) = (__u8)(d); } while(0)

#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)

#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))

 

 

/*

* CF-CARD IDE-HDD Support

*/

/* #define CONFIG_BFIN_TRUE_IDE */    /* Add CF flash card support */

/* #define CONFIG_BFIN_CF_IDE */    /* Add CF flash card support */

/* #define CONFIG_BFIN_HDD_IDE */    /* Add IDE Disk Drive (HDD) support */

 

#if defined(CONFIG_BFIN_CF_IDE) || defined(CONFIG_BFIN_HDD_IDE) || defined(CONFIG_BFIN_TRUE_IDE)

# define CONFIG_BFIN_IDE    1

# define CONFIG_CMD_IDE

#endif

 

#if defined(CONFIG_BFIN_IDE)

 

#define CONFIG_DOS_PARTITION    1

/*

* IDE/ATA stuff

*/

#undef  CONFIG_IDE_8xx_DIRECT    /* no pcmcia interface required */

#undef  CONFIG_IDE_LED        /* no led for ide supported */

#undef  CONFIG_IDE_RESET    /* no reset for ide supported */

 

#define CFG_IDE_MAXBUS        1    /* max. 1 IDE busses */

#define CFG_IDE_MAXDEVICE    (CFG_IDE_MAXBUS*1)    /* max. 1 drives per IDE bus */

 

#undef  CONFIG_EBIU_AMBCTL1_VAL

#define CONFIG_EBIU_AMBCTL1_VAL        0xFFC3FFC3

 

#define CONFIG_CF_ATASEL_DIS    0x20311800

#define CONFIG_CF_ATASEL_ENA    0x20311802

 

#if defined(CONFIG_BFIN_TRUE_IDE)

/*

* Note that these settings aren't for the most part used in include/ata.h

* when all of the ATA registers are setup

*/

#define CFG_ATA_BASE_ADDR    0x2031C000

#define CFG_ATA_IDE0_OFFSET    0x0000

#define CFG_ATA_DATA_OFFSET    0x0020    /* Offset for data I/O */

#define CFG_ATA_REG_OFFSET    0x0020    /* Offset for normal register accesses */

#define CFG_ATA_ALT_OFFSET    0x001C    /* Offset for alternate registers */

#define CFG_ATA_STRIDE        2    /* CF.A0 --> Blackfin.Ax */

#endif                /* CONFIG_BFIN_TRUE_IDE */

 

#if defined(CONFIG_BFIN_CF_IDE)    /* USE CompactFlash Storage Card in the common memory space */

#define CFG_ATA_BASE_ADDR    0x20211800

#define CFG_ATA_IDE0_OFFSET    0x0000

#define CFG_ATA_DATA_OFFSET    0x0000    /* Offset for data I/O */

#define CFG_ATA_REG_OFFSET    0x0000    /* Offset for normal register accesses */

#define CFG_ATA_ALT_OFFSET    0x000E    /* Offset for alternate registers */

#define CFG_ATA_STRIDE        1    /* CF.A0 --> Blackfin.Ax */

#endif                /* CONFIG_BFIN_CF_IDE */

 

#if defined(CONFIG_BFIN_HDD_IDE)    /* USE TRUE IDE */

#define CFG_ATA_BASE_ADDR    0x20314000

#define CFG_ATA_IDE0_OFFSET    0x0000

#define CFG_ATA_DATA_OFFSET    0x0020    /* Offset for data I/O */

#define CFG_ATA_REG_OFFSET    0x0020    /* Offset for normal register accesses */

#define CFG_ATA_ALT_OFFSET    0x001C    /* Offset for alternate registers */

#define CFG_ATA_STRIDE        2    /* CF.A0 --> Blackfin.A1 */

 

#undef  CONFIG_SCLK_DIV

#define CONFIG_SCLK_DIV        8

#endif                /* CONFIG_BFIN_HDD_IDE */

 

#endif                /*CONFIG_BFIN_IDE */

 

 

/*

* Misc Settings

*/

#define CONFIG_MISC_INIT_R

#define CONFIG_RTC_BFIN

#define CONFIG_UART_CONSOLE    0

 

/* #define CONFIG_BF537_VOIP_LEDCMD    1 */

 

/* Define if want to do post memory test */

#undef CONFIG_POST

#ifdef CONFIG_POST

#define FLASH_START_POST_BLOCK    11    /* Should > = 11 */

#define FLASH_END_POST_BLOCK    71    /* Should < = 71 */

#endif

 

 

/*

* Pull in common ADI header for remaining command/environment setup

*/

#include <configs/bfin_adi_common.h>

 

#include <asm/blackfin-config-post.h>

 

#endif

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2010-09-22 13:12:58     Re: uboot loader not working

Mike Frysinger (UNITED STATES)

Message: 93758   

 

please review the documentation:

http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:debugging

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2010-09-23 09:01:24     Re: uboot loader not working

Shyam sundar (INDIA)

Message: 93799   

 

I enabled the debug early serial option by defining #define CONFIG_DEBUG_EARLY_SERIAL in the serial.h file!

 

I do get "QST>" message printed on the hyperterminal!!

 

Why i am not able to get the other letters printed?

 

Since I am using a ldr,after the execution of the initcode routine, start.S should have been executed!

 

Can I know where i am going wrong?

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2010-09-23 15:24:45     Re: uboot loader not working

Mike Frysinger (UNITED STATES)

Message: 93807   

 

please read the document again.  if that is the last thing you see, then the only thing that executed was the initcode.  which usually means your external memory isnt working properly.

 

check your timings and verify you can read/write external memory sanely.

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2010-09-25 00:49:37     Re: uboot loader not working

Shyam sundar (INDIA)

Message: 93828   

 

I do get QST>

 

and then after every 40 seconds

 

ABCDEGHIJKLMNOPQST>

 

Can this problem be because of the ldr not written completely in the SPI flash?

 

I do have reverted back to the default settings! The SDRAM make is same as the one used in the EZ kit, except that the size i am using is 32MB.I have verified the SDRAM interface by testing it in VDSP environment.

 

Trying findout what could be the problem !!

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2010-09-28 09:14:29     Re: uboot loader not working

Shyam sundar (INDIA)

Message: 93906   

 

Can this thread be closed here? I have posted my queries in the U-boot help forum!!

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2010-09-28 11:04:35     Re: uboot loader not working

Mike Frysinger (UNITED STATES)

Message: 93911   

 

threads can easily be moved

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