2010-07-08 11:03:14     SPI access problem

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2010-07-08 11:03:14     SPI access problem

Timur Aydin (TURKEY)

Message: 91052   

 

Hi,

 

I have built the latest u-boot version from GIT (2010.06) and I use it with our BF537 based hardware. There is a M25P128 SPI EEPROM attached to the blackfin. u-boot boots successfully from this EEPROM. But when I write to the EEPROM using the "sf write" command, only 6 bytes or less are written successfully. When I attempt to write 7 bytes, incorrect data is written to the EEPROM. Here is the debug log of a transaction where I write 6 bytes (successfully) and then write 7 bytes (unsuccessfully)

 

 

 

First, the initial contents of the memory buffers:

 

bfin> md.b 1000000

01000000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................

01000010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................

01000020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................

01000030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................

bfin> md.b 1100000

01100000: 11 22 33 44 55 66 77 88 99 00 00 00 00 00 00 00    ."3DUfw.........

01100010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................

01100020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................

01100030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................

 

 

 

Here is the write/read transaction, writing 6 bytes:

 

 

bfin> sf write 1100000 40000 6

spi_claim_bus: bus:0 cs:1

PP: 0x01100000 => cmd = { 0x02 0x040000 } chunk_len = 6

spi_xfer: bus:0 cs:1 bitlen:8 bytes:1 flags:3

spi_cs_activate: SPI_FLG:fd02

spi_pio_xfer: tx:6 rx:ff

spi_cs_deactivate: SPI_FLG:ff02

spi_cs_deactivate: SPI_FLG:ff00

spi_xfer: bus:0 cs:1 bitlen:32 bytes:4 flags:1

spi_cs_activate: SPI_FLG:fd02

spi_pio_xfer: tx:2 rx:ff

spi_pio_xfer: tx:4 rx:ff

spi_pio_xfer: tx:0 rx:ff

spi_pio_xfer: tx:0 rx:ff

spi_xfer: bus:0 cs:1 bitlen:48 bytes:6 flags:2

spi_pio_xfer: tx:11 rx:ff

spi_pio_xfer: tx:22 rx:ff

spi_pio_xfer: tx:33 rx:ff

spi_pio_xfer: tx:44 rx:ff

spi_pio_xfer: tx:55 rx:ff

spi_pio_xfer: tx:66 rx:ff

spi_cs_deactivate: SPI_FLG:ff02

spi_cs_deactivate: SPI_FLG:ff00

spi_xfer: bus:0 cs:1 bitlen:8 bytes:1 flags:1

spi_cs_activate: SPI_FLG:fd02

spi_pio_xfer: tx:5 rx:ff

spi_xfer: bus:0 cs:1 bitlen:8 bytes:1 flags:0

spi_pio_xfer: tx:ff rx:0

spi_xfer: bus:0 cs:1 bitlen:0 bytes:0 flags:2

spi_cs_deactivate: SPI_FLG:ff02

spi_cs_deactivate: SPI_FLG:ff00

SF: STMicro: Successfully programmed 6 bytes @ 0x40000

spi_release_bus: bus:0 cs:1

bfin> sf read 1000000 40000 2000

spi_claim_bus: bus:0 cs:1

spi_xfer: bus:0 cs:1 bitlen:40 bytes:5 flags:1

spi_cs_activate: SPI_FLG:fd02

spi_pio_xfer: tx:b rx:ff

spi_pio_xfer: tx:4 rx:ff

spi_pio_xfer: tx:0 rx:ff

spi_pio_xfer: tx:0 rx:ff

spi_pio_xfer: tx:0 rx:ff

spi_xfer: bus:0 cs:1 bitlen:65536 bytes:8192 flags:2

spi_dma_xfer: doing half duplex RX

spi_cs_deactivate: SPI_FLG:ff02

spi_cs_deactivate: SPI_FLG:ff00

spi_release_bus: bus:0 cs:1

bfin> md.b 1000000

01000000: 11 22 33 44 55 66 ff ff ff ff ff ff ff ff ff ff    ."3DUf..........

01000010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................

01000020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................

01000030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................

 

 

Here is the write/read transation, writing 7 bytes. As can be seen at the end,

 

the data read is wrong:

 

bfin> sf write 1100000 40000 7

spi_claim_bus: bus:0 cs:1

PP: 0x01100000 => cmd = { 0x02 0x040000 } chunk_len = 7

spi_xfer: bus:0 cs:1 bitlen:8 bytes:1 flags:3

spi_cs_activate: SPI_FLG:fd02

spi_pio_xfer: tx:6 rx:ff

spi_cs_deactivate: SPI_FLG:ff02

spi_cs_deactivate: SPI_FLG:ff00

spi_xfer: bus:0 cs:1 bitlen:32 bytes:4 flags:1

spi_cs_activate: SPI_FLG:fd02

spi_pio_xfer: tx:2 rx:ff

spi_pio_xfer: tx:4 rx:ff

spi_pio_xfer: tx:0 rx:ff

spi_pio_xfer: tx:0 rx:ff

spi_xfer: bus:0 cs:1 bitlen:56 bytes:7 flags:2

spi_dma_xfer: doing half duplex TX

spi_cs_deactivate: SPI_FLG:ff02

spi_cs_deactivate: SPI_FLG:ff00

spi_xfer: bus:0 cs:1 bitlen:8 bytes:1 flags:1

spi_cs_activate: SPI_FLG:fd02

spi_pio_xfer: tx:5 rx:ff

spi_xfer: bus:0 cs:1 bitlen:8 bytes:1 flags:0

spi_pio_xfer: tx:ff rx:2

spi_xfer: bus:0 cs:1 bitlen:0 bytes:0 flags:2

spi_cs_deactivate: SPI_FLG:ff02

spi_cs_deactivate: SPI_FLG:ff00

SF: STMicro: Successfully programmed 7 bytes @ 0x40000

spi_release_bus: bus:0 cs:1

bfin> sf read 1000000 40000 2000

spi_claim_bus: bus:0 cs:1

spi_xfer: bus:0 cs:1 bitlen:40 bytes:5 flags:1

spi_cs_activate: SPI_FLG:fd02

spi_pio_xfer: tx:b rx:ff

spi_pio_xfer: tx:4 rx:ff

spi_pio_xfer: tx:0 rx:ff

spi_pio_xfer: tx:0 rx:ff

spi_pio_xfer: tx:0 rx:ff

spi_xfer: bus:0 cs:1 bitlen:65536 bytes:8192 flags:2

spi_dma_xfer: doing half duplex RX

spi_cs_deactivate: SPI_FLG:ff02

spi_cs_deactivate: SPI_FLG:ff00

spi_release_bus: bus:0 cs:1

bfin> md.b 1000000

01000000: 33 44 55 66 11 22 33 44 55 66 ff ff ff ff ff ff    3DUf."3DUf......

01000010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................

01000020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................

01000030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................

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2010-07-08 11:10:00     Re: SPI access problem

Timur Aydin (TURKEY)

Message: 91054   

 

One important difference between the <= 6 byte case and the > 6 byte case is that PIO transfer is used for <= 6 bytes and DMA is used for > 6 bytes. This can be seen in the debug logs.

 

 

 

Here is the result of the probe. There are actually 2 M25P128 SPI EEPROMS, one is used for normal boot, the other is used for recovery if the first one doesn't boot:

 

bfin> sf probe 1

spi_setup_slave: bus:0 cs:1 mmr:ffc00500 ctl:5c01 baud:3 flg:0

spi_claim_bus: bus:0 cs:1

spi_xfer: bus:0 cs:1 bitlen:8 bytes:1 flags:1

spi_cs_activate: SPI_FLG:fd02

spi_pio_xfer: tx:9f rx:ff

spi_xfer: bus:0 cs:1 bitlen:40 bytes:5 flags:2

spi_pio_xfer: tx:ff rx:20

spi_pio_xfer: tx:ff rx:20

spi_pio_xfer: tx:ff rx:18

spi_pio_xfer: tx:ff rx:0

spi_pio_xfer: tx:ff rx:0

spi_cs_deactivate: SPI_FLG:ff02

spi_cs_deactivate: SPI_FLG:ff00

SF: Got idcode 20 20 18 00 00

SF: Detected M25P128 with page size 256, total 16 MiB

spi_release_bus: bus:0 cs:1

16384 KiB M25P128 at 0:1 is now current device

 

 

bfin> sf probe 4

spi_setup_slave: bus:0 cs:4 mmr:ffc00500 ctl:5c01 baud:3 flg:0

spi_claim_bus: bus:0 cs:4

spi_xfer: bus:0 cs:4 bitlen:8 bytes:1 flags:1

spi_cs_activate: SPI_FLG:ef10

spi_pio_xfer: tx:9f rx:ff

spi_xfer: bus:0 cs:4 bitlen:40 bytes:5 flags:2

spi_pio_xfer: tx:ff rx:20

spi_pio_xfer: tx:ff rx:20

spi_pio_xfer: tx:ff rx:18

spi_pio_xfer: tx:ff rx:0

spi_pio_xfer: tx:ff rx:0

spi_cs_deactivate: SPI_FLG:ff10

spi_cs_deactivate: SPI_FLG:ff00

SF: Got idcode 20 20 18 00 00

SF: Detected M25P128 with page size 256, total 16 MiB

spi_release_bus: bus:0 cs:4

16384 KiB M25P128 at 0:4 is now current device

 

 

Given that u-boot boots correctly from this SPI EEPROM, I think read works correctly. The problem seems to be related to writes...

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2010-07-08 11:56:43     Re: SPI access problem

Timur Aydin (TURKEY)

Message: 91060   

 

Ok, I have prevented u-boot from using DMA by defining CONFIG_BFIN_SPI_NO_DMA. With this version, I was able to write 7 bytes without a problem. So, there seems to be a bug with SPI DMA...

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2010-07-08 12:51:21     Re: SPI access problem

Mike Frysinger (UNITED STATES)

Message: 91067   

 

the spi dma code is known to be broken at the moment.  the disable logic was lost when upgrading to 2010.06 though.

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