2010-04-18 14:33:53     bad CRC, dcplb miss, external memory addressing error

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2010-04-18 14:33:53     bad CRC, dcplb miss, external memory addressing error

anoob CS (INDIA)

Message: 88555   

 

Hi,

 

       NPLtsbf201561 board is a coustom board. It has two MT48LC32M16A2 SDRAM and S29GL512P  flash as shown in attachment. In this board it has 128 MB RAM, but showing 64 MB why?

 

1 . *** Warning - bad CRC, using default environment

 

2 . HWERRCAUSE: 0x3: external memory addressing error

3. EXCAUSE   : 0x26: dcplb miss

 

what these mean ?

 

I am showing the display came on hyperterminal below

 

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

 

U-Boot 2009.08 (ADI-2009R2-pre) (Apr 16 2010 - 15:49:52)

 

CPU:   ADSP bf561-0.5 (Detected Rev: 0.5) (parallel flash boot)

Board: NPLTSBF201561 board

Support: NO SUPPORT/

Clock: VCO: 500 MHz, Core: 500 MHz, System: 100 MHz

RAM:   64 MB

Flash: 64 MB

*** Warning - bad CRC, using default environment

 

In:    serial

Out:   serial

Err:   serial

Net:

 

Ack! Something bad happened to the Blackfin!

 

SEQUENCER STATUS:

SEQSTAT: 0000e026  IPEND: 8030  SYSCFG: 0032

  HWERRCAUSE: 0x3: external memory addressing error

  EXCAUSE   : 0x26: dcplb miss

  physical IVG15 asserted : <0x03fc055c> { _evt_default + 0x0 }

RETE: <0x03fc0004> { _start + 0x4 }

RETN: <0x03f9fe94> /* unknown address */

RETX: <0x03fd5792> { _smc91111_initialize + 0x3e }

RETS: <0x03fd577c> { _smc91111_initialize + 0x28 }

RETI: <0x03fd579e> { _smc91111_initialize + 0x4a }

DCPLB_FAULT_ADDR: <0x00002034> /* unknown address */

ICPLB_FAULT_ADDR: <0x03fcb250> { _fputs + 0x14 }

 

PROCESSOR STATE:

R0 : 0000003f    R1 : 03f9df25    R2 : 03f9fa70    R3 : 00000004

R4 : 08423e00    R5 : ffa0000c    R6 : 00000001    R7 : 00000000

P0 : 03fdfc9c    P1 : 00002150    P2 : 00002110    P3 : 03f9ff80

P4 : 00002118    P5 : 00002108    FP : 24100300    SP : 03f9fdc0

LB0: 03fc0cee    LT0: 03fc0cee    LC0: 00000000

LB1: 03fcee98    LT1: 03fcee92    LC1: 00000000

B0 : e93c73c3    L0 : 00000000    M0 : cd92701a    I0 : ffe01300

B1 : 493226ec    L1 : 00000000    M1 : 8d382e4e    I1 : 03f9fe8c

B2 : dcda2b4a    L2 : 00000000    M2 : ef5a7d58    I2 : 94b624fb

B3 : cdf22c7a    L3 : 00000000    M3 : 3f3822cb    I3 : 84922c42

A0.w: 00000060   A0.x: 00000000   A1.w: 00000060   A1.x: 00000000

USP : ff907ffc  ASTAT: 00000000

 

Hardware Trace:

   0 Target : <0x03fc0b00> { _bfin_panic + 0x0 }

     Source : <0x03fc05b2> { _evt_default + 0x56 }

   1 Target : <0x03fc055c> { _evt_default + 0x0 }

     Source : <0x03fd579c> { _smc91111_initialize + 0x48 }

   2 Target : <0x03fd5792> { _smc91111_initialize + 0x3e }

     Source : <0x03fc055a> { _trap + 0xba }

   3 Target : <0x03fc0504> { _trap + 0x64 }

     Source : <0x03fc0c66> { _trap_c + 0x12a }

   4 Target : <0x03fc0c0e> { _trap_c + 0xd2 }

     Source : <0x03fc0bf6> { _trap_c + 0xba }

   5 Target : <0x03fc0bd2> { _trap_c + 0x96 }

     Source : <0x03fc0b96> { _trap_c + 0x5a }

   6 Target : <0x03fc0b80> { _trap_c + 0x44 }

     Source : <0x03fc0b7a> { _trap_c + 0x3e }

   7 Target : <0x03fc0b68> { _trap_c + 0x2c }

     Source : <0x03fc0c86> { _trap_c + 0x14a }

   8 Target : <0x03fc0c74> { _trap_c + 0x138 }

     Source : <0x03fc0b4e> { _trap_c + 0x12 }

   9 Target : <0x03fc0b3c> { _trap_c + 0x0 }

     Source : <0x03fc0500> { _trap + 0x60 }

  10 Target : <0x03fc04a0> { _trap + 0x0 }

     Source : <0x03fd5790> { _smc91111_initialize + 0x3c }

  11 Target : <0x03fd578a> { _smc91111_initialize + 0x36 }

     Source : <0x03fd5780> { _smc91111_initialize + 0x2c }

  12 Target : <0x03fd577c> { _smc91111_initialize + 0x28 }

     Source : <0x03fcbc56> { _malloc + 0x48e }

  13 Target : <0x03fcbc4e> { _malloc + 0x486 }

     Source : <0x03fcb8f6> { _malloc + 0x12e }

  14 Target : <0x03fcb8f4> { _malloc + 0x12c }

     Source : <0x03fcbc06> { _malloc + 0x43e }

  15 Target : <0x03fcbbea> { _malloc + 0x422 }

     Source : <0x03fcbaa4> { _malloc + 0x2dc }

 

### ERROR ### Please RESET the board ###

 

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

 

 

 

 

 

 

 

I am also attaching <boardname.h> file

 

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

 

/*

* U-boot - Configuration file for BF561 NPLTSBF201561 board

*/

 

#ifndef __CONFIG_BF561_NPLTSBF201561_H__

#define __CONFIG_BF561_NPLTSBF201561_H__

 

#include <asm/config-pre.h>

 

 

/*

* Processor Settings

*/

#define CONFIG_BFIN_CPU             bf561-0.5

#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA

 

 

/*

* Clock Settings

*    CCLK = (CLKIN * VCO_MULT) / CCLK_DIV

*    SCLK = (CLKIN * VCO_MULT) / SCLK_DIV

*/

/* CONFIG_CLKIN_HZ is any value in Hz                    */

#define CONFIG_CLKIN_HZ            50000000

/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN        */

/*                                                1 = CLKIN / 2        */

#define CONFIG_CLKIN_HALF        0

/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass    */

/*                                                1 = bypass PLL    */

#define CONFIG_PLL_BYPASS        0

/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL        */

/* Values can range from 0-63 (where 0 means 64)            */

#define CONFIG_VCO_MULT            10

/* CCLK_DIV controls the core clock divider                */

/* Values can be 1, 2, 4, or 8 ONLY                    */

#define CONFIG_CCLK_DIV            1

/* SCLK_DIV controls the system clock divider                */

/* Values can range from 1-15                        */

#define CONFIG_SCLK_DIV            5

 

 

/*

* Memory Settings

*/

#define CONFIG_MEM_ADD_WDTH    9

#define CONFIG_MEM_SIZE        64

 

#define CONFIG_EBIU_SDRRC_VAL        0x306

#define CONFIG_EBIU_SDGCTL_VAL    0x91114d

 

#define CONFIG_EBIU_AMGCTL_VAL    0x18

#define CONFIG_EBIU_AMBCTL0_VAL    0x66138810

#define CONFIG_EBIU_AMBCTL1_VAL    0x88978897

 

#define CONFIG_SYS_MONITOR_LEN    (256 * 1024)

#define CONFIG_SYS_MALLOC_LEN    (128 * 1024)

 

 

/*

* Network Settings

*/

#define ADI_CMDS_NETWORK    1

#define CONFIG_NET_MULTI

#define CONFIG_SMC91111        1

#define CONFIG_SMC91111_BASE    0x24100300

#define CONFIG_SMC_USE_32_BIT    1

#define CONFIG_HOSTNAME        bf561-npltsbf201561

/* Uncomment next line to use fixed MAC address */

/* #define CONFIG_ETHADDR    02:80:ad:20:31:e8 */

 

 

/*

* Flash Settings

*/

#define CONFIG_SYS_FLASH_CFI        1

#define CONFIG_FLASH_CFI_DRIVER        1

#define CONFIG_SYS_FLASH_CFI_AMD_RESET

#define CONFIG_SYS_FLASH_BASE        0x20000000

#define CONFIG_SYS_MAX_FLASH_BANKS    1

#define CONFIG_SYS_MAX_FLASH_SECT    512

#define CONFIG_ENV_IS_IN_FLASH    1

#define CONFIG_ENV_ADDR        0x20004000

#define CONFIG_ENV_OFFSET    (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)

#define CONFIG_ENV_SIZE        0x2000

#define CONFIG_ENV_SECT_SIZE    0x20000    /*4000*/

#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)

#define ENV_IS_EMBEDDED

#else

#define CONFIG_ENV_IS_EMBEDDED_CUSTOM

#endif

#ifdef ENV_IS_EMBEDDED

/* WARNING - the following is hand-optimized to fit within

* the sector before the environment sector. If it throws

* an error during compilation remove an object here to get

* it linked after the configuration sector.

*/

# define LDS_BOARD_TEXT \

    cpu/blackfin/traps.o        (.text .text.*); \

    cpu/blackfin/interrupt.o    (.text .text.*); \

    cpu/blackfin/serial.o        (.text .text.*); \

    common/dlmalloc.o        (.text .text.*); \

    lib_generic/crc32.o        (.text .text.*); \

    lib_generic/zlib.o        (.text .text.*); \

    board/bf561-npltsbf201561/bf561-npltsbf201561.o    (.text .text.*); \

    . = DEFINED(env_offset) ? env_offset : .; \

    common/env_embedded.o        (.text .text.*);

#endif

 

 

/*

* I2C Settings

*/

#define CONFIG_SOFT_I2C

#ifdef CONFIG_SOFT_I2C

#define PF_SCL PF0

#define PF_SDA PF1

#define I2C_INIT \

    do { \

        *pFIO0_DIR |= PF_SCL; \

        SSYNC(); \

    } while (0)

#define I2C_ACTIVE \

    do { \

        *pFIO0_DIR |= PF_SDA; \

        *pFIO0_INEN &= ~PF_SDA; \

        SSYNC(); \

    } while (0)

#define I2C_TRISTATE \

    do { \

        *pFIO0_DIR &= ~PF_SDA; \

        *pFIO0_INEN |= PF_SDA; \

        SSYNC(); \

    } while (0)

#define I2C_READ ((*pFIO0_FLAG_D & PF_SDA) != 0)

#define I2C_SDA(bit) \

    do { \

        if (bit) \

            *pFIO0_FLAG_S = PF_SDA; \

        else \

            *pFIO0_FLAG_C = PF_SDA; \

        SSYNC(); \

    } while (0)

#define I2C_SCL(bit) \

    do { \

        if (bit) \

            *pFIO0_FLAG_S = PF_SCL; \

        else \

            *pFIO0_FLAG_C = PF_SCL; \

        SSYNC(); \

    } while (0)

#define I2C_DELAY        udelay(5)    /* 1/4 I2C clock duration */

 

#define CONFIG_SYS_I2C_SPEED        50000

#define CONFIG_SYS_I2C_SLAVE        0

#endif

 

 

/*

* Misc Settings

*/

#define CONFIG_UART_CONSOLE    0

 

 

/*

* Pull in common ADI header for remaining command/environment setup

*/

#include <configs/bfin_adi_common.h>

 

#endif

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

 

Thanks in advance

 

Anoob

 

flash.JPG

sdram.JPG

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2010-04-18 15:36:05     Re: bad CRC, dcplb miss, external memory addressing error

Mike Frysinger (UNITED STATES)

Message: 88556   

 

you probably didnt configure things correctly.  please read the documentation:

http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:porting

http://docs.blackfin.uclinux.org/doku.php?id=uclinux-dist:analyzing_traces

 

in fact, if you read the config file you posted, it obviously says "mem size is 64", not "128".

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2010-04-18 21:33:01     Re: bad CRC, dcplb miss, external memory addressing error

anoob CS (INDIA)

Message: 88557   

 

HI,

 

0x0000 0000-0x07FF FFFF (128 MB) Blackfin SDRAM.

 

/*

* Memory Settings

*/

#define CONFIG_MEM_ADD_WDTH    9

#define CONFIG_MEM_SIZE        64   

 

#define CONFIG_EBIU_SDRRC_VAL        0x306

#define CONFIG_EBIU_SDGCTL_VAL    0x91114d

 

#define CONFIG_EBIU_AMGCTL_VAL    0x18

#define CONFIG_EBIU_AMBCTL0_VAL    0x66138810

#define CONFIG_EBIU_AMBCTL1_VAL    0x88978897

 

#define CONFIG_SYS_MONITOR_LEN    (256 * 1024)

#define CONFIG_SYS_MALLOC_LEN    (128 * 1024)

 

///////////////////////////////////////////////////////////////////////////////////////////////////

 

I used to test u-boot by loading it to ram, goto start address. If i put 128 insted of 64 in (#define CONFIG_MEM_SIZE   64 )

 

the start address change from 0x07FC0000 insted of 0X03FC0000. But after loading to ram for testing,i am not able to see codes in 0x07FC0000 (if MEM_SIZE   128). if MEM_SIZE   64 , ican see code at 0X03FC0000, and display error as shown in above thread.

 

 

 

which values i have to modify ?

 

 

 

Thanks in advance,

 

Anoob

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2010-04-18 23:09:30     Re: bad CRC, dcplb miss, external memory addressing error

Mike Frysinger (UNITED STATES)

Message: 88561   

 

please read the documentation.  the README in the toplevel u-boot documents all the non-Blackfin options.

 

obviously MEM_SIZE of 64 makes no sense with 128 MB of ram.

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2010-04-29 22:04:46     Re: bad CRC, dcplb miss, external memory addressing error

anoob CS (INDIA)

Message: 89044   

 

Hi,

 

                I am a beginner/student  I have gone through README in the toplevel u-boot documents all the non-Blackfin options.

 

But where to change please specify.  In Memory Settings or Flash Settings or other.

 

Note: this board is custom and they are using this board with their other applications. In that they are using these values shown below.

 

EBIU_SDRRC_VAL    0x182

EBIU_SDGCTL_VAL   0x0091998F

 

EBIU_AMGCTL_VAL   0x18

EBIU_AMBCTL0_VAL  0x66138810

EBIU_AMBCTL1_VAL  0x88978897

 

 

 

There code is working fine!!!!!!

 

 

 

So I think this should work uboot code also

 

My Sdram is 128 MB and Flash is 64MB.

 

Settings in <boardname.h> for Sdram & Flash

 

//////////////////////////////////////////////////////////////////////////////

 

/*

* Memory Settings

*/

 

#define CONFIG_MEM_ADD_WDTH   10

#define CONFIG_MEM_SIZE       64

#define CONFIG_EBIU_SDRRC_VAL 0x182

#define CONFIG_EBIU_SDGCTL_VAL      0x0091998F

 

#define CONFIG_EBIU_AMGCTL_VAL      0x18

#define CONFIG_EBIU_AMBCTL0_VAL     0x66138810

#define CONFIG_EBIU_AMBCTL1_VAL     0x88978897

 

#define CFG_MONITOR_LEN       (256 * 1024)

#define CFG_MALLOC_LEN        (128 * 1024)

 

/*

* Flash Settings

*/

#define CFG_FLASH_CFI

#define CONFIG_FLASH_CFI_DRIVER

#define CFG_FLASH_CFI_AMD_RESET

#define CFG_FLASH_BASE        0x20000000

#define CFG_MAX_FLASH_BANKS   1

#define CFG_MAX_FLASH_SECT    512

#define CONFIG_ENV_IS_IN_FLASH      1

#define CONFIG_ENV_ADDR       0x20004000

#define CONFIG_ENV_OFFSET     (CONFIG_ENV_ADDR - CFG_FLASH_BASE)

#define CONFIG_ENV_SIZE       0x2000

#define CONFIG_ENV_SECT_SIZE  0x10000

#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)

#define ENV_IS_EMBEDDED

#else

#define ENV_IS_EMBEDDED_CUSTOM

#endif

 

/////////////////////////////////////////////////////////////////////////////////

 

I am in this problem for two months. Please help me.

 

Thanks in Advance

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2010-04-29 22:16:12     Re: bad CRC, dcplb miss, external memory addressing error

Mike Frysinger (UNITED STATES)

Message: 89045   

 

like i already said, if your board has 128 MB, why are you setting the define to 64 ?  please read the documentation.

 

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2010-04-29 23:00:21     Re: bad CRC, dcplb miss, external memory addressing error

anoob CS (INDIA)

Message: 89046   

 

Hi

 

When I set values as below

 

#define CONFIG_MEM_ADD_WDTH   10

 

#define CONFIG_MEM_SIZE       128

 

/*EBIU_SDBCTL = 0x2727*/

 

When I test by loading to ram, go to 3fc0000, run. nothing is coming.

 

But for #define CONFIG_MEM_SIZE 64 out is coming in HyperTerminal.

 

Once my uboot worked properly, but after third test it is not working (no change in settings)

 

 

 

 

 

Command worked: help, version ….

 

Then where may be the problem ?

 

Thanks in advance

 

Anoob C S

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2010-04-30 09:20:04     Re: bad CRC, dcplb miss, external memory addressing error

Mike Frysinger (UNITED STATES)

Message: 89064   

 

you need to verfy all of your new memory settings.  if you dont know how to calculate them, then do what the documetation ive already pointed you to:

https://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:porting

http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram

 

we cant help you if you continue to refuse to read the documentation

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2010-04-30 09:22:11     Re: bad CRC, dcplb miss, external memory addressing error

Mike Frysinger (UNITED STATES)

Message: 89065   

 

also, i dont know what version of u-boot you're working on as that is not a released version.  use either the latest release or latest svn trunk.  nothing else is supported.

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2010-05-04 22:42:21     Re: bad CRC, dcplb miss, external memory addressing error

anoob CS (INDIA)

Message: 89138   

 

Hi

 

now my uboot is working. I loaded the uboot.ldr.hex to flash and debugged using VDSP &  emulator  HPUSB-ICE.

 

I found that at reset the register EBIU_AMBCTL0 is FFC2FFC2, while execution step by step at the moment EBIU_AMBCTL0 changes (value in <boadname.h>) it hangs. so i gave value FFC2FFC2 and tested it is working!!!!!!!!.

 

Thank u for helping me.

 

Suggession for others having same problem.........

 

Give the worst case value and test it may work. then optmise the register and test.

 

sdram setting done by "bfsdccalculation_release_02.xls" from "https://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:porting"

 

Calculating DDR/SDRAM Settings

 

For assistance in calculating the Blackfin settings based on your memory's timings, please see the SDRAM page.

 

Let this thread help ouhers.

 

i am closing this thread

 

Thank you Mike Frysinger

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