2009-09-27 02:40:56     u-boot running on customed board based on bf533

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2009-09-27 02:40:56     u-boot running on customed board based on bf533

Nicole Otsuka (CHINA)

Message: 80510   

 

hi,

 

i'm gonna run u-boot.bin(complied by myself)  on bf533 but i met some problem

 

after programing the u-boot.bin to nor flash on my board, i powered on the board.

 

BUT....the minicom(or PUTTY) printed nothing for a long time,about 1 min....and then the console printed something like this:

 

< �| �<��|ǀ<�<�p?`8p|~< LMNOPQST>

Early:start.S: Relocate

Early:start.S: Zero BSS

Early:start.S: Lower to 15

 

 

AND stopped.......

 

i opened the early serial debug configuration in my bf533.h..so this info is correct to me...

 

BUT i dont know why it last such long time....

 

AND it stoped at the last of start.S.....i read the source of start.S ... i know it's waiting for 15interrupting.....and there is "raise 15"in the start.S ...why the interrupt cant be aroused??

 

i also tried bypassing the interrupt and jmping to the stage2 init directly....it can run stage 2 code and enter into the u-boot console.....

 

 

 

so....i have these two problem....it seams to be related to irq of bf533??

 

i'm not much exprience of u-boot, even in the stage1 level....

 

Can anyone help me?

 

 

 

and there is part of my configuration in bf533.h:

 

define CONFIG_BFIN_CPU             bf533-0.3

#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS

#define CONFIG_DEBUG_EARLY_SERIAL

#define CONFIG_DEBUG_DUMP_SYMS

 

#define CONFIG_CLKIN_HZ            24000000

#define CONFIG_CLKIN_HALF        0

#define CONFIG_PLL_BYPASS        0

#define CONFIG_VCO_MULT            33

#define CONFIG_CCLK_DIV            2

#define CONFIG_SCLK_DIV            6

 

#define CONFIG_MEM_ADD_WDTH    9

#define CONFIG_MEM_SIZE        32

 

#define CONFIG_EBIU_SDRRC_VAL    ((((CONFIG_SCLK_HZ / 1000) * 64) / 8192) - (4 + 2))

#define CONFIG_EBIU_SDGCTL_VAL    (SCTLE | PSS | TWR_2 | TRCD_3 | TRP_3 | TRAS_6 | PASR_ALL | CL_3)

#define CONFIG_EBIU_AMGCTL_VAL    0xFE

#define CONFIG_EBIU_AMBCTL0_VAL    0x7bb07bb0

#define CONFIG_EBIU_AMBCTL1_VAL    0x35507bb0

#define CONFIG_SYS_MONITOR_LEN    (256 * 1024)

#define CONFIG_SYS_MALLOC_LEN    (128 * 1024)

#define    CFG_SDRAM_BASE        0x00000000

 

#define ADI_CMDS_NETWORK    1

#define CONFIG_NET_MULTI

#define CONFIG_HOSTNAME        cm-bf533

/* Uncomment next line to use fixed MAC address */

/* #define CONFIG_ETHADDR    02:80:ad:20:31:e8 */

 

#define CONFIG_SYS_FLASH_BASE        0x20000000

#define CONFIG_SYS_MAX_FLASH_BANKS    1

#define CONFIG_SYS_MAX_FLASH_SECT    35

 

 

#define CONFIG_ENV_IS_IN_FLASH    1

 

#define CONFIG_ENV_OFFSET    0x40000

#define CONFIG_ENV_SECT_SIZE    0x10000

#define CONFIG_ENV_SIZE        0x10000

 

#define CONFIG_BAUDRATE        115200

#define CONFIG_RTC_BFIN

#define CONFIG_UART_CONSOLE    0

 

 

you can also tell me the incorrect configuration if exsisting..

 

 

 

Thank you,

 

Nicole

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2009-09-27 02:46:20     Re: u-boot running on customed board based on bf533

Nicole Otsuka (CHINA)

Message: 80512   

 

i, m so sorry  that i forgot to say .......the version of uboot is u-boot-2009.08 from truck-svn-2030

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2009-09-28 11:23:00     Re: u-boot running on customed board based on bf533

Robin Getz (UNITED STATES)

Message: 80568   

 

Nicole:

 

Did you review https://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:debugging

 

-Robin

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2009-09-28 21:55:47     Re: u-boot running on customed board based on bf533

Nicole Otsuka (CHINA)

Message: 80592   

 

thank you robin,

 

yes,i did.   i could understand the stage 1&stage 2's codes ,but i dont know what problem happens to them.

 

i did some debugging in the visualdsp via USB emulator....it worked different from when i running on the board....it seams to be looping within "while (bfin_read_EBIU_SDSTAT() & SDSRA)" and never jump out of the loop.

 

BUT if i reset the PC counter to the start address of Nor flash and do running serval times, it become better just like a normal u-boot starting....no long waiting before uart printing and no stopping after "raise 15".....

 

BUT if i reset the power of my board, the problem will return....

 

i'm trying to resolve this problem..but..if you have any idea or a better debugging way...please tell me...thank you.

 

 

 

btw, i also tried to use gdbproxy...but my emulator(blackshark 6 via USB) seams to be unsupported?

 

and.. i'm wanna use virtualbox to run visualdsp in a virtual Windows XP... but the virtual windows couldnt find the USB device.....is there any methos for using emulator in the vbox?

 

 

 

Best regards,

 

Nicole

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2009-09-29 04:55:53     Re: u-boot running on customed board based on bf533

Nicole Otsuka (CHINA)

Message: 80631   

 

i found if i load flash programing driver in the vdsp,  then change the pc counter to 0x20000000  and start running...u-boot will work well..without any waiting....

 

but... i dont know why.....is the configuration of sdc incorrect? i also read the bf533 and memory datasheet but i found nothing helpful to me....

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2009-10-06 03:51:04     Re: u-boot running on customed board based on bf533

Mike Frysinger (UNITED STATES)

Message: 80883   

 

ive seen this once or twice but havent been able to recreate it when i want to.  if u-boot is written to flash and the processor goes through a normal cold boot, then everything should just work.

 

otherwise you can try adding this line to cpu/blackfin/start.S right before the "lower to 15" line:

reti = [sp++];

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2009-11-04 16:21:43     Re: u-boot running on customed board based on bf533

Mike Frysinger (UNITED STATES)

Message: 82066   

 

sorry, other way around:

 

 

 

--- a/cpu/blackfin/start.S

+++ b/cpu/blackfin/start.S

@@ -76,7 +76,7 @@ ENTRY(_start)

    serial_early_puts("Init Registers");

 

    /* Disable self-nested interrupts and enable CYCLES for udelay() */

-   R0 = CCEN | 0x30;

+   R0 = SNEN | CCEN | 0x30;

    SYSCFG = R0;

 

    /* Zero out registers required by Blackfin ABI.

@@ -183,6 +183,12 @@ ENTRY(_start)

 

.Lnorelocate:

 

+   /* Some parts may already be at IVG15 w/out nested interrupts

+    * (like BF533 and BF561), so we need to make sure the raise

+    * below will work as expected.

+    */

+   [--sp] = reti;

+

    /* Setup the actual stack in external memory */

    sp.h = HI(CONFIG_STACKBASE);

    sp.l = LO(CONFIG_STACKBASE);

@@ -217,6 +223,7 @@ ENTRY(_start)

.Lenable_nested:

    cli r7;

    [--sp] = reti;

+   sp += 4;

    jump.l _cpu_init_f;

 

.LWAIT_HERE:

 

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