2009-05-27 16:33:02     bf527 EZ-Kit SDRAM Initialization

Document created by Aaronwu Employee on Sep 18, 2013
Version 1Show Document
  • View in full screen mode

2009-05-27 16:33:02     bf527 EZ-Kit SDRAM Initialization

Doug Bailey (UNITED STATES)

Message: 74670   

 

I recently inspected the OTP sectors of a BF527 EZ-Kit board.  I noticed that

all the preboot OTP sectors were set to 0 i.e. no special configuration.  (From

the manual I inferred that the preboot configuration starts in OTP page 0x18.)

 

bfin> otp read 1000000 18 6

OTP memory read: addr 0x01000000  page 0x018  count 6 ... ...... done

bfin> md.b 1000000 40

01000000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................

01000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................

01000020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................

01000030: 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55    UUUUUUUUUUUUUUUU

 

When I compile u-boot (1.1.6) and inspect the ldr file, I don't see any section

of code that would run in non-SDRAM that would set the SDRAM configuration

registers.

 

How do these registers get set before the code is loaded from FLASH? I see the

registers being written in the initcode function but this code appears to be

running in SDRAM (System.map has initcode @ 0x3fa1314)

 

What am I missing that performs the SDRAM configuration before code gets loaded

into SDRAM?

 

Thanks,

 

Doug Bailey

QuoteReplyEditDelete

 

 

2009-05-27 17:12:56     Re: bf527 EZ-Kit SDRAM Initialization

Mike Frysinger (UNITED STATES)

Message: 74675   

 

are you sure it built correctly ?  looks fine to me:

$ bfin-elf-ldr -qs u-boot-bf527-ezkit-para-2008R1.5.ldr

  DXE 1 at 0x00000000:

              Offset      BlockCode  Address    Bytes      Argument

    Block  1 0x00000000: 0xAD975001 0xFFA00000 0x00000000 0x0002B284 ( 8bit-dma-from-8bit ignore first )

    Block  2 0x00000010: 0xAD450801 0xFFA00000 0x0000009C 0xDEADBEEF ( 8bit-dma-from-8bit init )

 

if you want to know how u-boot initializes itself, the documentation covers that:

http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:debugging

QuoteReplyEditDelete

 

 

2009-05-27 18:08:37     Re: bf527 EZ-Kit SDRAM Initialization

Doug Bailey (UNITED STATES)

Message: 74676   

 

My bad.

 

I had compiled with changing the boot mode to bypass to assist with my using a background mode debugger.  When I defaulted back to BFIN_BOOT_PARA I saw the initcode section that gets loaded into L1 RAM.

 

QuoteReplyEditDelete

 

 

2009-05-27 18:20:39     Re: bf527 EZ-Kit SDRAM Initialization

Mike Frysinger (UNITED STATES)

Message: 74678   

 

right, there would be no initcode in the ldr from a bypass boot

QuoteReplyEditDelete

 

 

2009-05-28 12:21:37     Re: bf527 EZ-Kit SDRAM Initialization

Doug Bailey (UNITED STATES)

Message: 74714   

 

So I should be able to set

 

#define CONFIG_BFIN_BOOT_MODE         BFIN_BOOT_SPI_MASTER

 

recompile u-boot, load the resultant u-boot.ldr file into SPI FLASH (starting at offset 0) and then set the boot mode to SPI Serial boot (i.e. position 3).  The next time I reboot it should come up in u-boot.

QuoteReplyEditDelete

 

 

2009-05-28 12:24:58     Re: bf527 EZ-Kit SDRAM Initialization

Mike Frysinger (UNITED STATES)

Message: 74716   

 

you might want to do `make clean` first, but otherwise, in general, yes

QuoteReplyEditDelete

 

 

2009-05-28 17:02:04     Re: bf527 EZ-Kit SDRAM Initialization

Doug Bailey (UNITED STATES)

Message: 74728   

 

Works as advertized.

 

Now I want to confirm my understanding of the preboot section.  I have written what I believe is a valid configuration to the OTP pages 18, 19 and 1A.

 

When I perform a "monitor reset" reset with my JTAG debugger and dump the SDRAM registers, I see the reset values in these registers.  Am I correct in presuming that the the debugger exception is such that it is not allowing the on-board boot ROM to load the preboot values?

 

In any case, what is the best way to validate that the settings I am placing in the preboot OTP are valid and as expected?  Is there any way to do this with a JTAG debugger?

 

****** My preboot values for bf527 ez-kit:

 

bfin> otp read 1000000 18 20

OTP memory read: addr 0x01000000  page 0x018  count 32 ... ................................ done

bfin> md.b 1000000 30

01000000: 00 00 00 20 03 03 84 07 00 00 00 00 00 09 00 00    ... ............

01000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................

01000020: 8d 99 11 80 25 00 00 00 00 00 00 00 00 00 00 00    ....%...........

QuoteReplyEditDelete

 

 

2009-05-28 17:21:19     Re: bf527 EZ-Kit SDRAM Initialization

Mike Frysinger (UNITED STATES)

Message: 74731   

 

the problem with most JTAG debuggers is that they themselves program the memory controller and other registers for you.  first make sure that is not occurring.

 

since i cant really speak to what your JTAG device is doing, i'll use general terms.  when you reset the part, it'll start at the on-chip rom (0xEF000000).  from there, it'll execute the preboot (still in on-chip rom) which involves reading OTP and doing stuff based on what it says to.  only then will it proceed to process the LDR code from whatever boot source you have configured.

 

so really, the best way to test would be to have the init section of LDR execute an emuexcpt instruction.  this will signal the JTAG immediately upon execution and wait there.  or create a while (1){} loop and have the part wait for you to connect.

 

otherwise, this is the only method currently for validating OTP that i'm aware of.  i dont believe there are any utilities to assist in this endeavor.  i'll ask around, but otherwise i'll open a tracker item to create one.

 

btw, these questions arent really tied to any software, so you may want to send queries to the analog.com site.

http://forms.analog.com/Form_Pages/support/dsp/dspSupport.asp

QuoteReplyEditDelete

Attachments

    Outcomes