2009-03-05 02:30:55     Data cache problem on bf547

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2009-03-05 02:30:55     Data cache problem on bf547

watson xu (CHINA)

Message: 70405   

 

hello, everyone,

 

I'm using BF547 rev 0.1 on my application, with Micrel KSZ8842 ethernet controller. u-boot has ported to my board, and it works fine, but the problem is the ethernet will not work when the data cache enabled, when i disable the dcache using "dcache off" command, the ethernet then works.

 

i notice that the pulse width of the AMS1 is different when the dcache enable or not.   it would be  about 168ns with data cache enabled, and 330ns when dcache is disabled.

 

my u-boot is based on the u-boot-2008.10 and BF548-EZKIT, the AM bus configuration is just the same as BF548-EZKIT except the EBIU_AMBCTL1 = 0xFFC27BB0, KS8842 seems require more wait cycle when access the ethernet port.

 

the same condition will happen in uClinux, i have to disable the data cache, otherwise the ethernet will not work fine.

 

how to resolve this problem?

 

 

 

thanks in advance.

 

 

 

ks884x.c

ks884x.h

bf547-apm.h

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2009-03-05 03:29:19     Re: Data cache problem on bf547

watson xu (CHINA)

Message: 70417   

 

and here is the schematic about the ethernet controller.

 

the io memory range is 0x24000300 - 0x2400030f.

and on my board it is connect without EEPROM, which is differ with the schematic, and be sure to work.

 

output.pdf

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2009-03-07 19:04:48     Re: Data cache problem on bf547

Robin Getz (UNITED STATES)

Message: 70564   

 

Watson:

 

>BF547 rev 0.1

 

Isn't supported - it has a bug in it that is not possible to workaround in the Linux  kernel (or anything that uses external memory).

 

-Robin

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2009-03-09 02:23:51     Re: Data cache problem on bf547

watson xu (CHINA)

Message: 70573   

 

Thank you, Robin!

 

I have found where the problem is, it is not the bf547 problem.

 

when enable the cache, the operation to the ethernet port become more faster, and cause the ksz8842 crash.  I add some delay after write to this chip, then the problem resolved.

 

Now, u-boot works fine with dcache enabled. i'm porting it to uClinux now.

 

 

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2009-03-09 08:29:12     Re: Data cache problem on bf547

Rutger Hofman (NETHERLANDS)

Message: 70606   

 

We also have planned BF547 rev 0.1 on our board (see https://blackfin.uclinux.org/gf/project/toolchain/forum/?action=ForumBrowse&forum_id=44&thread_id=31154&_forum_action=ForumMessageBrowse). We intend to memory-map Ethernet (an NE2000 clone) and the connection to an FPGA.

 

Are we in trouble then? What are the problems with BF547 rev 0.1 exactly? We have just got the first samples so we can port u-boot. Should we switch to another cpu, like BF548 which is pin-compatible?

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2009-03-09 16:42:22     Re: Data cache problem on bf547

Mike Frysinger (UNITED STATES)

Message: 70624   

 

it isnt bf547 specific, it is all bf54x for rev 0.1.  look at the anomaly sheet for anomaly 448.

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