2009-02-02 11:15:19     The most updated u-boot can't work on my board, why?

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2009-02-02 11:15:19     The most updated u-boot can't work on my board, why?

Zhi Qiang Zhang (CHINA)

Message: 68679   

 

Hi,

 

I made a BF531 board that use HY57V641620HG as the SDRAM, and it uses a 22.5792MHz crystal. The u-boot-1.1.5 can work on this board, but the most updated version(revision 1632) of u-boot can't work.

 

The definition should be like this,

 

#define CONFIG_CLKIN_HZ                 22579200

/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN             */

/*                                                1 = CLKIN / 2         */

#define CONFIG_CLKIN_HALF               0

/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass     */

/*                                                1 = bypass PLL        */

#define CONFIG_PLL_BYPASS               0

/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL              */

/* Values can range from 0-63 (where 0 means 64)                        */

#define CONFIG_VCO_MULT                 17

/* CCLK_DIV controls the core clock divider                             */

/* Values can be 1, 2, 4, or 8 ONLY                                     */

#define CONFIG_CCLK_DIV                 1

/* SCLK_DIV controls the system clock divider                           */

/* Values can range from 1-15                                           */

#define CONFIG_SCLK_DIV                 4

 

 

 

#define CONFIG_MEM_SIZE         32

/* Early EZKITs had 32megs, but later have 64megs */

#if (CONFIG_MEM_SIZE == 64)

# define CONFIG_MEM_ADD_WDTH    10

#else

# define CONFIG_MEM_ADD_WDTH    9

#endif

 

#define CONFIG_EBIU_SDRRC_VAL   ((((CONFIG_SCLK_HZ / 1000) * 64) / 8192) - (5 + 2))

#define CONFIG_EBIU_SDGCTL_VAL  (SCTLE | PSS | TWR_2 | TRCD_2 | TRP_2 | TRAS_5 | PASR_ALL | CL_3)

 

#define CONFIG_EBIU_AMGCTL_VAL  (AMBEN_ALL)

#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)

#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)

 

#define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for monitor */

#define CFG_MALLOC_LEN          (128 * 1024)    /* Reserve 128 kB for malloc() */

 

 

 

Is there something wrong in the SDRAM register setting?

 

 

 

Regards,

 

ZhangZQ

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2009-02-02 11:40:23     Re: The most updated u-boot can't work on my board, why?

Mike Frysinger (UNITED STATES)

Message: 68683   

 

you can check the sdram settings yourself:

http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram

 

as for debugging problems, please read the documentation:

http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:debugging

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