2009-01-18 22:19:48     VDSP load u-boot

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2009-01-18 22:19:48     VDSP load u-boot

jacqueline liu (CHINA)

Message: 68076   

 

Hi .

 

i'm using a BF527 EZ-KIT board .and i'm using the Flash Programmer of VDSP5.0 to load the u-boot to the board .

 

My problem is that when i reset the board , i can only get strange words but not  the right information from the uart1.

 

i've tried different baudrate ,but none is useful .

 

would you please tell me what's the problem of it .

 

thanks .

 

 

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2009-01-18 22:31:57     Re: VDSP load u-boot

Mike Frysinger (UNITED STATES)

Message: 68077   

 

the default baudrate is 57600 and is what all of our release images use.  if you arent getting that, then check the board settings and your serial cable to make sure they're correct.

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2009-01-19 00:09:39     Re: VDSP load u-boot

jacqueline liu (CHINA)

Message: 68080   

 

i've tried the baudrate as 57600, but it doesn't work . the words i've got are a lot of strange words and never stop .

 

should i change any thing of the code or something special that should be take care of ?

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2009-01-19 00:16:22     Re: VDSP load u-boot

jacqueline liu (CHINA)

Message: 68081   

 

i'm using the defaults setting of the config file as follow:

 

#ifndef __CONFIG_BF527_EZKIT_H__

#define __CONFIG_BF527_EZKIT_H__

 

#include <asm/blackfin-config-pre.h>

 

 

/*

* Processor Settings

*/

#define CONFIG_BFIN_CPU             bf527-0.0

#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA

 

 

/*

* Clock Settings

* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV

* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV

*/

/* CONFIG_CLKIN_HZ is any value in Hz     */

#define CONFIG_CLKIN_HZ   25000000

/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN  */

/*                                                1 = CLKIN / 2  */

#define CONFIG_CLKIN_HALF  0

/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass */

/*                                                1 = bypass PLL */

#define CONFIG_PLL_BYPASS  0

/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL  */

/* Values can range from 0-63 (where 0 means 64)   */

#define CONFIG_VCO_MULT   21

/* CCLK_DIV controls the core clock divider    */

/* Values can be 1, 2, 4, or 8 ONLY     */

#define CONFIG_CCLK_DIV   1

/* SCLK_DIV controls the system clock divider    */

/* Values can range from 1-15      */

#define CONFIG_SCLK_DIV   4

 

 

/*

* Memory Settings

*/

#define CONFIG_MEM_ADD_WDTH 10

#define CONFIG_MEM_SIZE  64

 

#define CONFIG_EBIU_SDRRC_VAL 0x03F6

#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS)

#define CONFIG_EBIU_SDBCTL_VAL (EBE | EBSZ_64 | EBCAW_10)

 

#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL)

#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)

#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)

 

#define CFG_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for monitor */

#define CFG_MALLOC_LEN  (384 * 1024) /* Reserve 384 kB for malloc() (video/spi are big) */

#define CFG_GBL_DATA_SIZE 0x4000

 

/*

* NAND Settings

* (can't be used sametime as ethernet)

*/

/* #define CONFIG_BFIN_NFC */

#ifdef CONFIG_BFIN_NFC

#define CFG_BFIN_NFC_CTL_VAL 0x0033

#define CFG_NAND_BASE  0 /* not actually used */

#define CFG_MAX_NAND_DEVICE 1

#define NAND_MAX_CHIPS  1

#define ADI_CMDS_EXTRA  CFG_CMD_NAND

#endif

 

/*

* Network Settings

*/

#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \

    !defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC)

#define ADI_CMDS_NETWORK 1

#define CONFIG_BFIN_MAC

#define CONFIG_BFIN_MAC_RMII

#define CONFIG_NETCONSOLE 1

#define CONFIG_NET_MULTI 1

#endif

#define CONFIG_HOSTNAME  bf527-ezkit

/* Uncomment next line to use fixed MAC address */

/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */

 

 

/*

* Flash Settings

*/

#define CFG_FLASH_BASE  0x20000000

#define CFG_FLASH_CFI  /* The flash is CFI compatible */

#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */

#define CFG_FLASH_PROTECTION

#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */

#define CFG_MAX_FLASH_SECT 259 /* max number of sectors on one chip */

 

#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)

#define CFG_ENV_IS_IN_EEPROM 1

#define CFG_ENV_OFFSET  0x4000

#else

#define CFG_ENV_IS_IN_FLASH 1

#define CFG_ENV_ADDR  0x20004000

#define CFG_ENV_OFFSET  (CFG_ENV_ADDR - CFG_FLASH_BASE)

#endif

#define CFG_ENV_SIZE  0x2000

#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */

#define ENV_IS_EMBEDDED_CUSTOM

 

/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider  */

/* Values can range from 2-65535     */

/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)    */

#define CONFIG_SPI

#define CONFIG_SPI_BAUD   2

#define CONFIG_SPI_BAUD_INITBLOCK 4

 

 

/*

* I2C Settings

*/

#define CONFIG_HARD_I2C  1 /* I2C TWI */

#define CFG_I2C_SPEED  50000

#define CFG_I2C_SLAVE  0

 

 

/*

* Misc Settings

*/

#define CONFIG_RTC_BFIN

#define CONFIG_MISC_INIT_R

#define CONFIG_UART_CONSOLE 1

 

#define CONFIG_BFIN_COMMANDS \

( CFG_BFIN_CMD_BOOTLDR | \

   CFG_BFIN_CMD_CPLBINFO | \

   CFG_BFIN_CMD_OTP )

 

/* Don't waste time transferring a logo over the UART */

#if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)

# define CONFIG_VIDEO

#endif

 

 

/*

* Pull in common ADI header for remaining command/environment setup

*/

#include <configs/bfin_adi_common.h>

 

#include <asm/blackfin-config-post.h>

 

#endif

 

 

 

 

is anything of it that i have to change ?

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2009-01-19 03:17:24     Re: VDSP load u-boot

Mike Frysinger (UNITED STATES)

Message: 68084   

 

use the release image on our website first to verify things before attempting to compile u-boot yourself

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2009-01-19 04:19:23     Re: VDSP load u-boot

jacqueline liu (CHINA)

Message: 68095   

 

Hi

 

i'm using the source code that download from your web site .

 

nothing's changed .

 

it's not work ,so i wonder if anything needed to be changed .

 

may any problem when i using the VDSP5.0?

 

i used the project included in the VDSP example .Flash Programmer of the STMicroelectronics M29W320DB/EB flash device.

 

load driver in the Tools->Flash Programmer->driver .

 

program the data u-boot.ldr.hex in the Tools->Flash Programmer->programming with the file format of Intel Hex.

 

is there anything missing or wrong?

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2009-01-19 04:31:04     Re: VDSP load u-boot

jacqueline liu (CHINA)

Message: 68096   

 

and i also tried the fill u-boot-bf527-ezkit-para-2008R1.5.ldr download from the web site .

 

program it with the binary file format .

 

it still does not work .

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2009-01-19 09:53:00     Re: VDSP load u-boot

Mike Frysinger (UNITED STATES)

Message: 68107   

 

we dont know/use/support VDSP.  the only VDSP information you can find is in the wiki:

http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:loading

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2009-01-19 09:54:21     Re: VDSP load u-boot

Mike Frysinger (UNITED STATES)

Message: 68108   

 

then check your hardware like i said

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2009-01-19 19:58:08     Re: VDSP load u-boot

jacqueline liu (CHINA)

Message: 68130   

 

ok

 

i'll try that.

 

thanks

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