2008-09-19 14:20:31     u-boot 1.1.6, bf561, custom board and spi flash

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2008-09-19 14:20:31     u-boot 1.1.6, bf561, custom board and spi flash

Thomas Langås (NORWAY)

Message: 62446   

 

I have a custom board with BF561 and a SPI Flash from Spansion (www.spansion.com/datasheets/S25FL008A_00_B2_e.pdf). I've written my u-boot.ldr to the spi flash, and I know the code from initcode.c is started, as I programmed two leds to light up, and I see the serial early-parts.  However, it doesn't seem to do much after initcode.c is done, so my question is: what is supposed to be executed after that?  According to this https://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:debugging it start.S that is next.  I added code inside start.S:_start() to turn off the LEDs, but it doesn't appear to be executed:

 

        P0.L = LO(FIO0_FLAG_S);

        P0.H = HI(FIO0_FLAG_S);

        R0.L = 0x9800;

        w[P0] = R0.L;

 

And, also, I don't get any more serial early-parts after the initcode.c-part is done.  So, any suggestion of what to check / change / test to figure out what happens after initcode.c is done executing?

 

In advance, thanks!

 

--

Thomas

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2008-09-19 15:20:47     Re: u-boot 1.1.6, bf561, custom board and spi flash

Mike Frysinger (UNITED STATES)

Message: 62448   

 

i'd tell you to hook up JTAG and find out where it's hung in the bootrom, but that wont work on the BF561

 

we havent been able to validate BF561 SPI flash yet (since the BF561-EZKIT sucks) ... but things you should check:

- ldr flags ... you need to make sure your ldr has the bits set in its header to match your flash

- memory settings ... in your initcode, try rurnning some external memory tests to make sure your settings are correct

 

if you can change the bmode and have jtag, you could also try booting u-boot using gdb/jtag so as to cut out the SPI flash steps and make sure the rest works first

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2008-09-19 16:08:11     Re: u-boot 1.1.6, bf561, custom board and spi flash

Thomas Langås (NORWAY)

Message: 62453   

 

Here's a dump of the flags (should it be 24-bit flash instead of 8-bit flash?):

 

tlan@sarissa:~/src/external/u-boot/trunk/u-boot-1.1.6$ bfin-elf-ldr u-boot.ldr

Showing LDR u-boot.ldr ...

  LDR header: A00000DE ( 8-bit-flash wait:15 hold:3 spi:500K )

  DXE 1 at 0x00000000:

    Block  1 at 0x00000000

         Addr: 0xFFA00000 Bytes: 0x000003FC Flags: 0x000A ( resvect init )

    Block  2 at 0x00000406

         Addr: 0xFFA00000 Bytes: 0x0000000C Flags: 0x0002 ( resvect )

    Block  3 at 0x0000041C

         Addr: 0x07FC0000 Bytes: 0x00003BCC Flags: 0x0002 ( resvect )

    Block  4 at 0x00003FF2

         Addr: 0x00000000 Bytes: 0x00002000 Flags: 0x0012 ( resvect ignore )

    Block  5 at 0x00005FFC

         Addr: 0x07FC3BCC Bytes: 0x00004434 Flags: 0x0002 ( resvect )

    Block  6 at 0x0000A43A

         Addr: 0x07FC8000 Bytes: 0x00008000 Flags: 0x0002 ( resvect )

    Block  7 at 0x00012444

         Addr: 0x07FD0000 Bytes: 0x00008000 Flags: 0x0002 ( resvect )

    Block  8 at 0x0001A44E

         Addr: 0x07FD8000 Bytes: 0x000064BC Flags: 0x0002 ( resvect )

    Block  9 at 0x00020914

         Addr: 0xFFA0000C Bytes: 0x00000028 Flags: 0x0002 ( resvect )

    Block 10 at 0x00020946

         Addr: 0x07FDE4E4 Bytes: 0x00006940 Flags: 0x8003 ( zerofill resvect final )

 

 

Regarding the memory-settings; I have run tests through my jtag adapter (ICEbear from section5.ch) so they seem correct, but maybe I could include some testcode at the end of initcode.c to check if the memory-settings are correct when run from the SPI-image.

 

Regarding the bmode/jtag, I can change the bmode to whatever I'd like, and I have the ICEbear jtag.  Should I get u-boot running if I do:

* Create a small elf that initializes the cpu, memory-settings and things, and then breaks out and back to the gdbproxy/jtag-interface.

* Load u-boot.bin at some address (does this have to be fixed, or can I just choose 0x1000 for instance?) and start it.

 

I tried the above scenario, but I only changed the registers through the gdb-settings, and didn't run the ssync / idle-commands after setting the pll-registers. Is that a must to get the core accept the settings, or will they effect if I just wait long enough?

 

--

Thomas

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2008-09-19 16:30:58     Re: u-boot 1.1.6, bf561, custom board and spi flash

Mike Frysinger (UNITED STATES)

Message: 62454   

 

the u-boot docs online show you how to load u-boot over jtag properly

 

there is no "24-bit flash" ... those settings are for parallel flash only i think

 

you may have to toggle with the SPI load speed ... or maybe not

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2008-09-23 04:55:54     Re: u-boot 1.1.6, bf561, custom board and spi flash

Thomas Langås (NORWAY)

Message: 62547   

 

I tried to follow the information found here:

https://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:debugging

 

However, this is the result:

 

(bfin-jtag-gdb) load debuginit.elf

Loading section .text, size 0x40c lma 0xffa00000

Start address 0xffa00000, load size 1036

Transfer rate: 23086 bits/sec, 345 bytes/write.

(bfin-jtag-gdb) c

Continuing.

[New thread 1]

 

Program received signal SIGTRAP, Trace/breakpoint trap.

bfin_reset () at reset.c:30

30              __builtin_bfin_ssync();

(bfin-jtag-gdb) load u-boot

Loading section .text, size 0x13b44 lma 0x7fc0000

Loading section .rodata, size 0x5fb4 lma 0x7fd3b44

Loading section .data, size 0x43f8 lma 0x7fd9af8

Loading section .u_boot_cmd, size 0x5cc lma 0x7fddef0

Loading section .text_l1, size 0x28 lma 0x7fde4bc

Start address 0x7fc0000, load size 124132

Transfer rate: 265807 bits/sec, 508 bytes/write.

(bfin-jtag-gdb) call memset(&_bss_start, 0, &_bss_end - &_bss_start)

 

Program received signal SIGEMT, Emulation trap.

0x00001001 in ?? ()

The program being debugged was signaled while in a function called from GDB.

GDB remains in the frame where the signal was received.

To change this behavior use "set unwindonsignal on"

Evaluation of the expression containing the function (memset) will be abandoned.

(bfin-jtag-gdb) c

Continuing.

 

Program received signal SIGEMT, Emulation trap.

0x00001001 in ?? ()

(bfin-jtag-gdb) monitor reset

(bfin-jtag-gdb) load debuginit.elf

Loading section .text, size 0x40c lma 0xffa00000

Start address 0xffa00000, load size 1036

Transfer rate: 51478 bits/sec, 345 bytes/write.

(bfin-jtag-gdb) c

Continuing.

 

Program received signal SIGTRAP, Trace/breakpoint trap.

bfin_reset () at reset.c:30

30              __builtin_bfin_ssync();

(bfin-jtag-gdb) load u-boot

Loading section .text, size 0x13b44 lma 0x7fc0000

Loading section .rodata, size 0x5fb4 lma 0x7fd3b44

Loading section .data, size 0x43f8 lma 0x7fd9af8

Loading section .u_boot_cmd, size 0x5cc lma 0x7fddef0

Loading section .text_l1, size 0x28 lma 0x7fde4bc

Start address 0x7fc0000, load size 124132

Transfer rate: 260987 bits/sec, 508 bytes/write.

(bfin-jtag-gdb) c

Continuing.

 

Program received signal SIGEMT, Emulation trap.

0x00001001 in ?? ()

(bfin-jtag-gdb)

 

The loading of debuginit.elf works nicely, as I can see the word "SBLACKIHFN>"

on my console. The code for the debuginit.elf is according to the webpage above:

#include <asm/blackfin.h>

 

.global __start

 

__start:

        sp.l = LO(L1_SRAM_SCRATCH_END - 20);

        sp.h = HI(L1_SRAM_SCRATCH_END - 20);

        call _initcode;

1:

        emuexcpt;

        jump 1b;

 

.size __start, .-__start

 

 

It was compiled with:

bfin-elf-gcc -nostartfiles debuginit.S cpu/blackfin/initcode.o -o debuginit.elf -Iinclude -D__ASSEMBLY__ -mcpu=bf561

 

I'm having a hard time figuring out what's wrong, so any pointers at all would be greatly

appreciated.  It seems like the blackfin reads the SPI like it should (considering that

I get the same output from booting from SPI Flash as I do when loading debuginit.elf.

 

Here's my config.h for building/configuring u-boot:

/*

* U-boot - Configuration file for Norbit WBMS Motherboard Rev.2 (BF561)

*/

 

#ifndef __CONFIG_NORBIT_WBMS_REV2_H__

#define __CONFIG_NORBIT_WBMS_REV2_H__

 

#include <asm/blackfin-config-pre.h>

 

/*

* Which revision is this config for

*/

#define NORBIT_WBMS_REV             2

 

/*

* Processor Settings

*/

#define CONFIG_BFIN_CPU             bf561-0.5

#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER

 

/* Enable serial during bootup */

#define CONFIG_DEBUG_EARLY_SERIAL 1

#define CONFIG_BAUDRATE            115200

 

/*

* Clock Settings

*    CCLK = (CLKIN * VCO_MULT) / CCLK_DIV

*    SCLK = (CLKIN * VCO_MULT) / SCLK_DIV

*/

/* CONFIG_CLKIN_HZ is any value in Hz                    */

#define CONFIG_CLKIN_HZ            20000000

/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN        */

/*                                                1 = CLKIN / 2        */

#define CONFIG_CLKIN_HALF        0

/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass    */

/*                                                1 = bypass PLL    */

#define CONFIG_PLL_BYPASS        0

/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL        */

/* Values can range from 0-63 (where 0 means 64)            */

#define CONFIG_VCO_MULT            25

/* CCLK_DIV controls the core clock divider                */

/* Values can be 1, 2, 4, or 8 ONLY                    */

#define CONFIG_CCLK_DIV            1

/* SCLK_DIV controls the system clock divider                */

/* Values can range from 1-15                        */

#define CONFIG_SCLK_DIV            5

 

 

/*

* Memory Settings

*/

#define CONFIG_MEM_SIZE        128

 

        /* SDRAM Refresh Rate Control Register - EBIU_SDRRC */

        /*   RDIV = ((fSCLK * tREF) / NRA) - (tRAS + tRP)*/

        /*      fSCLK = 100 * 10^6 */

        /*      tREF = 64 * 10^-3 */

        /*      NRA = 8192  */

        /*      tRAS = 6 */

        /*      tRP = 3 */

        /*   RDIV = 772.25 => 772 => 0x304 */

#define CONFIG_EBIU_SDRRC_VAL    0x304

#define CONFIG_EBIU_SDGCTL_VAL     0x119989  //PSS | TWR_2 | TRCD_3 | TRP_3 | TRAS_6 | PASR_ALL | CL_2 | SCTLE

#define CONFIG_EBIU_SDBCTL_VAL    0x27

 

#define CONFIG_EBIU_AMGCTL_VAL    0x000F

#define CONFIG_EBIU_AMBCTL0_VAL    0xFFC2FFC2

#define CONFIG_EBIU_AMBCTL1_VAL    0xFFC2FFC2

 

#define CFG_MONITOR_LEN        (384 * 1024)    /* Reserve 256 kB for monitor */

#define CFG_MALLOC_LEN        (256 * 1024)    /* Reserve 128 kB for malloc() */

 

 

/*

* Network Settings

*/

#define ADI_CMDS_NETWORK    1

#define CONFIG_DRIVER_SMC91111    1

#define CONFIG_SMC91111_BASE    0x24000300

#define CONFIG_SMC_USE_32_BIT    1

#define CONFIG_HOSTNAME        norbit-wbms

/* Uncomment next line to use fixed MAC address */

/* #define CONFIG_ETHADDR    02:80:ad:20:31:e8 */

 

 

/*

* Flash Settings

*/

#define CFG_FLASH_CFI        /* The flash is CFI compatible */

#define CFG_FLASH_CFI_DRIVER    /* Use common CFI driver */

#define CFG_FLASH_CFI_AMD_RESET

#define CFG_FLASH_BASE        0x20000000

#define CFG_MAX_FLASH_BANKS    1    /* max number of memory banks */

#define CFG_MAX_FLASH_SECT    512    /* max number of sectors on one chip */

 

/* We boot with u-boot in SPI Flash */

#define CFG_ENV_IS_IN_EEPROM    1

#define CFG_ENV_OFFSET          0x4000

#define CFG_ENV_HEADER          (CFG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */

#define CFG_ENV_SIZE            0x2000

#define CFG_ENV_SECT_SIZE       0x10000  /* Total Size of Environment Sector */

#define ENV_IS_EMBEDDED_CUSTOM  /* BOOT_MODE is SPI_MASTER */

 

/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider    */

/* Values can range from 2-65535                */

/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)            */

#define CONFIG_SPI

#define CONFIG_SPI_BAUD            2

#define CONFIG_SPI_BAUD_INITBLOCK    4

 

 

/*

* Misc Settings

*/

#define CONFIG_UART_CONSOLE    0

 

#define CONFIG_BFIN_COMMANDS \

    ( CFG_BFIN_CMD_CPLBINFO )

 

 

/*

* Pull in common ADI header for remaining command/environment setup

*/

#include <configs/bfin_adi_common.h>

 

#include <asm/blackfin-config-post.h>

 

#endif                /* __CONFIG_EZKIT561_H__ */

 

 

--

Thomas

 

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2008-09-23 11:55:07     Re: u-boot 1.1.6, bf561, custom board and spi flash

Mike Frysinger (UNITED STATES)

Message: 62563   

 

if things crashed when accessing external memory, you need to check your memory settings

 

and when things crashed, check the state of the CEC to see why it's crashing

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2008-09-24 07:57:37     Re: u-boot 1.1.6, bf561, custom board and spi flash

Thomas Langås (NORWAY)

Message: 62627   

 

Now I've set the BMODE to BYPASS and changed u-boot config to reflect this (and programmed u-boot.bin into my regular flash located at 0x20000000), and now this is what I get on my console:

 

Early:start.S: Init Registers

Early:start.S: Find ourselves

Early:start.S: Program Clocks

SBLA!CK!IHFN>

Early:start.S: Relocate

Early:start.S: Zero BSS

EEarly:start.S: Init Registers

Early:start.S: Find ourselves

Early:start.S: Program Clocks

SB

 

The extra E above (on line with "Init Registers") is from the cpu/blackfin/start.S line with:

serial_early_puts("Lower to 15");

 

It seems to crash and reboot on the above line, and then it failes to get to the line that prints out the L the second time it's inside initcode.c, and then it just hangs.

 

--

Thomas

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2008-09-24 15:28:42     Re: u-boot 1.1.6, bf561, custom board and spi flash

Mike Frysinger (UNITED STATES)

Message: 62647   

 

when it lowers to 15, that is when execution actually starts in external memory.  before that point, everything is executing out of flash.  before that early puts call, that is when the stack is moved from on-chip to external memory, so that may have crashed as well.  this just indicates that your external memory is still not configured properly.

 

do you have jtag/gdb ?  if so, you should connect to the part, reset it, load the init.elf (see the debugging page), and run some manual tests on external memory (like writing out a pattern and then read it back).  then check the CEC/sequencer status after each test to make sure things worked.

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2008-09-26 07:34:29     Re: u-boot 1.1.6, bf561, custom board and spi flash

Thomas Langås (NORWAY)

Message: 62790   

 

The test itself worked like it should (I modified the initcode.c to write to SDRAM, and then readback the values written, and it didn't return any errors).

 

My question is: how do I read back the SEQSTAT-register from within gdb?  (I assume that's the CEC/sequence status you're talking about?)

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2008-09-26 14:02:04     Re: u-boot 1.1.6, bf561, custom board and spi flash

Mike Frysinger (UNITED STATES)

Message: 62810   

 

you can find example gdb snippets in our toolchain svn:

debug-helpers/gdb-scripts/bfin

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2008-09-29 07:35:44     Re: u-boot 1.1.6, bf561, custom board and spi flash

Thomas Langås (NORWAY)

Message: 62891   

 

Ok, so here's the output from console:

 

Early:start.S: Init Registers

Early:start.S: Find ourselves

Early:start.S: Program Clocks

SBLA!CK!IHFN>

Early:start.S: Relocate

Early:start.S: Zero BSS

 

And here's the output from gdb:

 

(gdb) regs_norete

R0: 200002c8 536871624     P0: ffe0203c      RETS: 200001a6

R1: 00000000 0             P1: 07fa01e8      RETI: 07fa01f0

R2: 00000000 0             P2: ffe02104      RETX: 200002c8

R3: 07fc6718 133981976     P3: 00008000      RETE: void

R4: 07fa0000 133824512     P4: 07fa01f0      RETN: 16182016

R5: 20000000 536870912     P5: ffb00ff0     ASTAT: 00000021

R6: 00000000 0             SP: 07f5ff7c        CC: 00000001

R7: 200002c8 536871624    USP: f04eb000   SEQSTAT: 0000c021

PC: ffa0011c 0             FP: 07f5ff7c    SYSCFG: 00000032

(gdb) show_cec

IMASK: 0x0000801f

IPEND: 0x00008019

ILAT:  0x00000020

(gdb) seqstat

SEQSTAT: 0000c021

EXCAUSE:    0x21       (undef inst)

SFTRESET:   0x0        (last reset was not a software reset)

HWERRCAUSE: 0x2        (system mmr error)

(gdb) show_clocks

PLL_LOCKCNT: 0x0300

VR_CTL:      0x00eb

PLL_DIV:     0x0005

PLL_CTL:     0xb200

(gdb) show_sdram_561

SDRRC:  0x0306

SDBCTL: 0x00000027

bank 0: (enabled) (10-bit) (128MB)

bank 1: (disabled) (8-bit) (16MB)

bank 2: (disabled) (8-bit) (16MB)

bank 3: (disabled) (8-bit) (16MB)

SDSTAT: 0x0019  (SDC busy) (in self-refresh) (powerup sequence) (SDRAM powered up) (EAB - No error detected) (Bus granted)

SDGCTL: 0x0011114a

 

(I added a new regs-function called regs_norete to be used when rete is void)

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