2007-09-11 16:17:48     Changed SDRAM on BF537 Stamp to 128MB

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2007-09-11 16:17:48     Changed SDRAM on BF537 Stamp to 128MB

Bob Peret (UNITED STATES)

Message: 44048    <pre wrap="">I have changed the SDRAM chips on my 537 Stamp board from the MT48LC32M8A2 chips

to MT48LC64M8A2. These chips are 16M x 8 x 4 banks (512 Mbits). They have 2048

columns (the previous chips had 1024 columns). I am trying to modify u-boot to

see the additional memory. The stamp continues to function with no

modifications, but only has 64MB (as expected).

 

I have changed the following in include/configs/bf537.h:

 

//#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */

//#define CONFIG_MEM_ADD_WDTH 10 /* 8, 9, 10, 11 */

 

// MT48LC64M8A2 512Mb, 4 x 128Mb banks, 8192 rows x 2048 columns x 8 bits

#define CONFIG_MEM_SIZE 128

#define CONFIG_MEM_ADD_WDTH 11

 

Uboot still runs but thinks there is only 64MB of memory. If I change:

 

//#define CFG_MAX_RAM_SIZE 0x04000000

#define CFG_MAX_RAM_SIZE 0x08000000

Then Uboot never starts (no console output)

Looking at the 537 HW reference manual, it looks like this size device should be

able to work. What am I forgetting to set? Looking at the SDRAM chip specs,

CAS latency is the same, and the chips look very similar. Any help would be

greatly appreciated.

 

Bob Peret

 

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2007-10-07 10:22:07     Re: Changed SDRAM on BF537 Stamp to 128MB

Mark T (UNITED STATES)

Message: 45029    Hello, I am experiencing the same problem. I have defined new SDRAM chips in mem_init.h but system only boots if I configure it for 64MB, with 128 no luck at all. BF537 rev 0.2, 2 x MT48LC64M8A2 on a custom board with u-Boot 2007R1-RC3. Thanks, Mark

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2007-10-07 14:42:24     Re: Changed SDRAM on BF537 Stamp to 128MB

Mark T (UNITED STATES)

Message: 45031    Ok, problem resolved, I forgot to modify the linker file... Mark

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2007-10-08 11:54:47     Re: Changed SDRAM on BF537 Stamp to 128MB

Robin Getz (UNITED STATES)

Message: 45063    Bob/Mark:

 

There is a bug in the Blackfin that effectively limits the amount of memory that is avalible. You need BF537 0.3 or later.

 

See the faq:

 

http://docs.blackfin.uclinux.org/doku.php?id=faq

 

and look for "BF533 board only shows ~60meg free with 128meg"

 

-Robin

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2007-10-08 12:14:09     Re: Changed SDRAM on BF537 Stamp to 128MB

Mark T (UNITED STATES)

Message: 45065    Yes, I am aware of that "anomaly", the rest of the protos will be 1.0.3 Thanks, Mark

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2008-06-23 09:29:03     Re: Changed SDRAM on BF537 Stamp to 128MB

Mark Urup (DENMARK)

Message: 57730   

 

I'm having the same problem, but can't seem to get it working.

 

I'm running a custom board, based on the bf537-stamp design. I get no console output when running a 128mb version of uboot.

I must be missing something.

 

It u-boot 1.1.6 (2008R1)

 

Could you post the changes you made?

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2008-06-23 09:44:19     Re: Changed SDRAM on BF537 Stamp to 128MB

Mike Frysinger (UNITED STATES)

Message: 57732   

 

the changes needed for 2007R1 and 2008R1 are very different.  the latter is much easier to get things working.

 

please read: http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:debugging

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2008-06-24 03:46:35     Re: Changed SDRAM on BF537 Stamp to 128MB

Mark Urup (DENMARK)

Message: 57756   

 

After turning on debugging I get:

 

## Starting application at 0x01000000 ...

Early:start.S: Init Registers

Early:start.S: Relocate

E

 

 

 

and then it hangs.

 

After reading in "cpu/blackfin/start.S", it's where u-boots loads itself into the end of ram.

 

I just don't understand what other options I need to set to use the extra memory!?

 

 

 

I've changed the same options as Bob, but as far as I can see in the mem_init.h file, there is no option for col. addressing width (which has changed from 1024 to 2048).

 

 

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2008-06-24 04:05:13     Re: Changed SDRAM on BF537 Stamp to 128MB

Mike Frysinger (UNITED STATES)

Message: 57760   

 

there is no mem_init.h header file in 2008R1 ... you need to set the EBIU config registers yourself

 

http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:porting

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2008-06-30 09:30:09     Re: Changed SDRAM on BF537 Stamp to 128MB

Mark Urup (DENMARK)

Message: 58119   

 

I just grabbed a copy of the lastest stable build, and the latest snapshot, and in both files (u-boot-1.1.6-2008R1.tar.bz2, and u-boot-trunk-svn.src.tar.bz2), mem_init.h still exists (cpu/blackfin/mem_init.h).

 

Is is just no longer used, or being phased out?

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2008-06-30 09:50:14     Re: Changed SDRAM on BF537 Stamp to 128MB

Mike Frysinger (UNITED STATES)

Message: 58123   

 

i thought i'd deleted it before 2008R1, but apparently not

 

pretend it doesnt exist

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2008-07-02 02:32:00     Re: Changed SDRAM on BF537 Stamp to 128MB

Mark Urup (DENMARK)

Message: 58176   

 

Help, i'm out of idea's!

 

It makes no difference if I set the registers myself.

 

It still does not work.

 

#define CONFIG_EBIU_AMGCTL_VAL          0xFF

#define CONFIG_EBIU_AMBCTL0_VAL         0x7BB07BB0

#define CONFIG_EBIU_AMBCTL1_VAL         0x7BB07BB0

 

#define SDRAM_NRA       8192

#define SDRAM_TREF      64

#define SDRAM_TRAS      TRAS_1

#define SDRAM_TRP       TRP_1

#define SDRAM_TWR       TWR_2

#define SDRAM_CAS       CL_3

#define SDRAM_TRCD      TRCD_1

 

#define CONFIG_EBIU_SDRRC_VAL (((CONFIG_SCLK_HZ/1000)*SDRAM_TREF)/SDRAM_NRA)-(SDRAM_TRAS-SDRAM_TRP)

#define CONFIG_EBIU_SDBCTL_VAL  EBCAW_10 | EBSZ_128 | EBE

#define CONFIG_EBIU_SDGCTL_VAL  PSSE | SDRAM_TWR | SDRAM_TRCD | SDRAM_TRP | SDRAM_TRAS | PASR_ALL | SDRAM_CAS | SCTLE

 

The thing that make my head spin is that I can boot u-boot with these settings, no problem, but it still reports only 64 mb of ram.

If I then change the CONFIG_MEM_SIZE from 64 to 128 mb, it does not boot anymore. Loading the u-boot.bin file gives:

Early:start.S: Init Registers

Early:start.S: Relocate

E

 

Where it hangs...

 

Loading u-boot via visual dsp (dxe file) gives:

Early:start.S: Init Registers

Early:start.S: Relocate

Early:start.S: Zero BSS

Early:start.S: Lower to 15

Early: NOP Slide

Early: Board init flash

Early: Init CPLB tables

Early: Exceptions setup

Early: Turn on ICACHE

Early: Turn on DCACHE

Early: Init global data

Early: IRQ init

Early: Environment init

Early: Baudrate init

Early: Serial init

Early: Console init flash

Early: End of early debugging

 

 

U-Boot 1.1.6 (ADI-2008R1) (Jul  2 2008 - 08:14:17)

 

CPU:   ADSP bf537-0.3 (Detected Rev: 0.3)

Board: IP Thinking ipt-shark537

       For support go to: http://ipthinking.dk or

                          http://blackfin.uclinux.org

Clock: VCO: 600 MHz, Core: 600 MHz, System: 120 MHz

RAM:   64 MB

33 erase regions found, only 4 used

Flash:  0 kB

DCPLB exception outside of memory map at 0x74400000

 

 

Ack! Something bad happened to the Blackfin!

 

SEQUENCER STATUS:

SEQSTAT: 0000e026  IPEND: 3fc0164  SYSCFG: 0032

  HWERRCAUSE: 0x3

  EXCAUSE   : 0x26

  physical IVG6 asserted : <0x03fc0810> { _evt_default + 0x0 }

  physical IVG8 asserted : <0x03fc0810> { _evt_default + 0x0 }

RETE: <0x03fc0004> { _start + 0x4 }

RETN: <0x07d89bb0> { ___udivdi3 + 0x3dac3dc }

RETX: <0x03fc116e> { _malloc + 0x44a }

RETS: <0x03fd6ad8> { _NewHandle + 0x14 }

PC  : <0x03fc0164> { _start + 0x164 }

DCPLB_FAULT_ADDR: <0x746f6f60> { ___udivdi3 + 0x7071978c }

ICPLB_FAULT_ADDR: <0x03fc116e> { _malloc + 0x44a }

 

PROCESSOR STATE:

R0 : 746f6f51    R1 : 0000000f    R2 : 746f6f50    R3 : 00000002

R4 : 03fe5d08    R5 : 00000011    R6 : 00000004    R7 : 00000004

P0 : 00000000    P1 : 746f6f50    P2 : 746f6f60    P3 : 03fe5d10

P4 : 00000000    P5 : 03f5c000    FP : 03fe5d08    SP : 03f5bddc

LB0: 03fdd6e8    LT0: 03fdd6dc    LC0: 00000000

LB1: 03fc68be    LT1: 03fc68bc    LC1: 00000000

B0 : 00000000    L0 : 00000000    M0 : 00000000    I0 : 00000033

B1 : 00000000    L1 : 00000000    M1 : 00000000    I1 : 03f5bf36

B2 : 00000000    L2 : 00000000    M2 : ff807ffc    I2 : 07d899bc

B3 : 00000000    L3 : 00000000    M3 : 00000000    I3 : 00000000

A0.w: 00000000   A0.x: 00000000   A1.w: 00000000   A1.x: 00000000

USP : 004f6e6c  ASTAT: 00000000

 

Hardware Trace:

   0 Target : <0x03fc0584> { _bfin_panic + 0x0 }

     Source : <0x03fc0652> { _trap_c + 0x92 }

   1 Target : <0x03fc0650> { _trap_c + 0x90 }

     Source : <0x03fd5f8a> { _printf + 0x42 }

   2 Target : <0x03fd5f80> { _printf + 0x38 }

     Source : <0x03fc097c> { _serial_puts + 0x1c }

   3 Target : <0x03fc0970> { _serial_puts + 0x10 }

     Source : <0x03fc094c> { _serial_putc + 0x48 }

   4 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

   5 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

   6 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

   7 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

   8 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

   9 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

  10 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

  11 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

  12 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

  13 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

  14 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

  15 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

 

Please reset the board

 

### ERROR ### Please RESET the board ###

 

The initdram function is exactly like the example in the wiki page.

 

I've looked through the linker script, but that didn't give me any new clues.

 

 

What am I missing?

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2008-07-02 08:18:43     Re: Changed SDRAM on BF537 Stamp to 128MB

Mike Frysinger (UNITED STATES)

Message: 58217   

 

that does not look like a memory problem, it looks like you've misconfigured your flash settings

 

make sure your parallel flash settings in your board config match your hardware

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2008-07-07 05:55:06     Re: Changed SDRAM on BF537 Stamp to 128MB

Mark Urup (DENMARK)

Message: 58411   

 

I don't think so, first off, the flash works fine (but why I get the notice, I don't know).

 

But just to be sure, I compiled and loaded a version of u-boot without nand support, this was the result:

 

Early:start.S: Init Registers

Early:start.S: Relocate

Early:start.S: Zero BSS

Early:start.S: Lower to 15

Early: NOP Slide

Early: Board init flash

Early: Init CPLB tables

Early: Exceptions setup

Early: Turn on ICACHE

Early: Turn on DCACHE

Early: Init global data

Early: IRQ init

Early: Environment init

Early: Baudrate init

Early: Serial init

Early: Console init flash

Early: End of early debugging

 

 

U-Boot 1.1.6 (ADI-2008R1) (Jul  7 2008 - 11:41:38)

 

CPU:   ADSP bf537-0.3 (Detected Rev: 0.3)

Board: IP Thinking ipt-shark537

       For support go to: http://ipthinking.dk or

                          http://blackfin.uclinux.org

Clock: VCO: 600 MHz, Core: 600 MHz, System: 120 MHz

RAM:   64 MB

Flash:  0 kB

DCPLB exception outside of memory map at 0x74400000

 

 

Ack! Something bad happened to the Blackfin!

 

SEQUENCER STATUS:

SEQSTAT: 0000e026  IPEND: 3fc0164  SYSCFG: 0032

  HWERRCAUSE: 0x3

  EXCAUSE   : 0x26

  physical IVG6 asserted : <0x03fc0810> { _evt_default + 0x0 }

  physical IVG8 asserted : <0x03fc0810> { _evt_default + 0x0 }

RETE: <0x03fc0004> { _start + 0x4 }

RETN: <0x004ca000> /* unknown address */

RETX: <0x03fc116e> { _malloc + 0x44a }

RETS: <0x03fd2e1c> { _NewHandle + 0x14 }

PC  : <0x03fc0164> { _start + 0x164 }

DCPLB_FAULT_ADDR: <0x746f6f60> { ___smulsi3_highpart + 0x7071dfd4 }

ICPLB_FAULT_ADDR: <0x03fc116e> { _malloc + 0x44a }

 

PROCESSOR STATE:

R0 : 746f6f51    R1 : 0000000f    R2 : 746f6f50    R3 : 00000002

R4 : 03fdf508    R5 : 00000011    R6 : 00000004    R7 : 00000004

P0 : 00000000    P1 : 746f6f50    P2 : 746f6f60    P3 : 03fdf510

P4 : 00000000    P5 : 03f5c000    FP : 03fdf508    SP : 03f5bddc

LB0: 03fd8f54    LT0: 03fd8f48    LC0: 00000000

LB1: 03fc68be    LT1: 03fc68bc    LC1: 00000000

B0 : 00000000    L0 : 00000000    M0 : 00000000    I0 : 00000033

B1 : 00000000    L1 : 00000000    M1 : 00000000    I1 : 03f5bf36

B2 : 00000000    L2 : 00000000    M2 : ff807ffc    I2 : 00000000

B3 : 00000000    L3 : 00000000    M3 : 00000000    I3 : 00000000

A0.w: 00392a71   A0.x: 00000000   A1.w: 00005e3f   A1.x: 00000000

USP : 0057fe44  ASTAT: 00000000

 

Hardware Trace:

   0 Target : <0x03fc0584> { _bfin_panic + 0x0 }

     Source : <0x03fc0652> { _trap_c + 0x92 }

   1 Target : <0x03fc0650> { _trap_c + 0x90 }

     Source : <0x03fd22ce> { _printf + 0x42 }

   2 Target : <0x03fd22c4> { _printf + 0x38 }

     Source : <0x03fc097c> { _serial_puts + 0x1c }

   3 Target : <0x03fc0970> { _serial_puts + 0x10 }

     Source : <0x03fc094c> { _serial_putc + 0x48 }

   4 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

   5 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

   6 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

   7 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

   8 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

   9 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

  10 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

  11 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

  12 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

  13 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

  14 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

  15 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

 

Please reset the board

 

### ERROR ### Please RESET the board ###

 

Another thing I noticed, is that u-boot still reports only 64 MB, but it is compiled for 128 (CONFIG_MEM_SIZE = 128)

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2008-07-07 06:36:20     Re: Changed SDRAM on BF537 Stamp to 128MB

Mark Urup (DENMARK)

Message: 58412   

 

Just a note: Our design is based on the v2.2 BF537 STAMP board. This is able to run with 128MB ram, right?

 

"Mark T" talks about modifying a linker file. Is this still necessary?

 

On our board u-boot is stored in a serial flash, and the linux system in parallel flash.

As far as I can read, it shouldn't be necessary to modify the linker file/script (but then again, I don't know if this falls under the catagory "really weird").

 

If I disable ENV_IS_EMBEDDED (while still having nand disabled), I get:

 

Early:start.S: Init Registers

Early:start.S: Relocate

Early:start.S: Zero BSS

Early:start.S: Lower to 15

Early: NOP Slide

Early: Board init flash

Early: Init CPLB tables

Early: Exceptions setup

Early: Turn on ICACHE

Early: Turn on DCACHE

Early: Init global data

Early: IRQ init

Early: Environment init

Early: Baudrate init

Early: Serial init

Early: Console init flash

Early: End of early debugging

 

 

U-Boot 1.1.6 (ADI-2008R1) (Jul  7 2008 - 11:41:38)

 

CPU:   ADSP bf537-0.3 (Detected Rev: 0.3)

Board: IP Thinking ipt-shark537

       For support go to: http://ipthinking.dk or

                          http://blackfin.uclinux.org

Clock: VCO: 600 MHz, Core: 600 MHz, System: 120 MHz

RAM:   64 MB

Flash:  0 kB

DCPLB exception outside of memory map at 0x65400000

 

 

Ack! Something bad happened to the Blackfin!

 

SEQUENCER STATUS:

SEQSTAT: 0000e026  IPEND: 3fc0164  SYSCFG: 0032

  HWERRCAUSE: 0x3

  EXCAUSE   : 0x26

  physical IVG6 asserted : <0x03fc0810> { _evt_default + 0x0 }

  physical IVG8 asserted : <0x03fc0810> { _evt_default + 0x0 }

RETE: <0x03fc0004> { _start + 0x4 }

RETN: <0x004ca000> /* unknown address */

RETX: <0x03fc0e4c> { _malloc + 0x128 }

RETS: <0x03fd2e1c> { _NewHandle + 0x14 }

PC  : <0x03fc0164> { _start + 0x164 }

DCPLB_FAULT_ADDR: <0x65746180> { ___smulsi3_highpart + 0x6176d1f4 }

ICPLB_FAULT_ADDR: <0x03fc0e4c> { _malloc + 0x128 }

 

PROCESSOR STATE:

R0 : 65746161    R1 : 65746160    R2 : 65746170    R3 : 3366a8c0

R4 : 00000258    R5 : 00000011    R6 : 0000001c    R7 : 00000004

P0 : 00000010    P1 : 65746160    P2 : 65746180    P3 : 03fdf510

P4 : 03f5c02e    P5 : 03f5c000    FP : 03fdf508    SP : 03f5bddc

LB0: 03fd8f54    LT0: 03fd8f48    LC0: 00000000

LB1: 03fc68be    LT1: 03fc68bc    LC1: 00000000

B0 : 00000000    L0 : 00000000    M0 : 00000000    I0 : 00000033

B1 : 00000000    L1 : 00000000    M1 : 00000000    I1 : 00000400

B2 : 00000000    L2 : 00000000    M2 : ff807ffc    I2 : 00000000

B3 : 00000000    L3 : 00000000    M3 : 00000000    I3 : 00000000

A0.w: 0039293b   A0.x: 00000000   A1.w: 00005d09   A1.x: 00000000

USP : 0057fe44  ASTAT: 00000000

 

Hardware Trace:

   0 Target : <0x03fc0584> { _bfin_panic + 0x0 }

     Source : <0x03fc0652> { _trap_c + 0x92 }

   1 Target : <0x03fc0650> { _trap_c + 0x90 }

     Source : <0x03fd22ce> { _printf + 0x42 }

   2 Target : <0x03fd22c4> { _printf + 0x38 }

     Source : <0x03fc097c> { _serial_puts + 0x1c }

   3 Target : <0x03fc0970> { _serial_puts + 0x10 }

     Source : <0x03fc094c> { _serial_putc + 0x48 }

   4 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

   5 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

   6 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

   7 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

   8 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

   9 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

  10 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

  11 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

  12 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

  13 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

  14 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

  15 Target : <0x03fc0938> { _serial_putc + 0x34 }

     Source : <0x03fc0944> { _serial_putc + 0x40 }

 

Please reset the board

 

### ERROR ### Please RESET the board ###

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2008-07-07 09:58:10     Re: Changed SDRAM on BF537 Stamp to 128MB

Robin Getz (UNITED STATES)

Message: 58416   

 

Mark:

 

At one point in time we had a board with 128M on it - let me see if I can track it down again.

 

 

 

-Robin

QuoteReplyEditDelete

 

 

2008-07-10 04:06:25     Re: Changed SDRAM on BF537 Stamp to 128MB

Mark Urup (DENMARK)

Message: 58595   

 

any news on this matter?

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2008-07-14 03:22:25     Re: Changed SDRAM on BF537 Stamp to 128MB

Mark Urup (DENMARK)

Message: 58745   

 

Thanks for all the help; the problem is resolved.

 

It was a problem with  the EBIU_SDGCTL_VAL register that was not set correctly.

 

Also, if anyone runs into the same problem, and you like us are booting of a built-in flash, you need to write the new u-boot into the flash, because otherwise it does not change the EBIU_SDBCTL_VAL register.

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2008-07-14 22:23:17     Re: Changed SDRAM on BF537 Stamp to 128MB

Mike Frysinger (UNITED STATES)

Message: 58783   

 

with 2008R1+, there should be no need really to touch the linker script.  the default one is pretty flexible and in this specific case you're working on, it should be fine.

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2008-07-14 22:23:29     Re: Changed SDRAM on BF537 Stamp to 128MB

Mike Frysinger (UNITED STATES)

Message: 58784   

 

changing the EBIU registers is considered part of the "reprogramming of clocks" and currently u-boot only does that when executing out of flash.  loading into external memory and then doing "go" will not change clocks/memory settings.

 

you could cheat and program some later sectors of flash (like 0x20200000) and then do a "go" on that address ... that way you still have a known working version to boot from at 0x20000000 ...

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