2008-06-06 10:49:45     uboot, jfss2 and environment on single spi-flash device

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2008-06-06 10:49:45     uboot, jfss2 and environment on single spi-flash device

Marco Rohleder (GERMANY)

Message: 56816   

 

Hi !

 

I have a custom BF561 board.

 

It is equipped with 32MBit SPI-Flash.

 

On the first 2 sectors (128kB) the Uboot is stored and booting from there.

 

I want also to store the environment settings there and use the free space for a jffs2.

 

It that possible?

 

I did he following changes on the original bf561-ezkit.h :

 

Changed CONFIG_BFIN_BOOT_MODE to BFIN_BOOT_SPI_MASTER

 

Added #define CONFIG_SPI and copied the spi_flash.c from 537stamp directory to bf561 ezkit directory. Also added the spi_flash.o in the makefile there.

 

BF561 boots fine.

 

Changed CFG_IS_IN_FLASH to CFG_ENV_IS_IN_EEPROM.

 

That is working, what i dont understand is, what this means ( derived from bf548-ezkit.h ):

 

#define CFG_ENV_ADDR  0x20004000

#define CFG_ENV_OFFSET ( CFG_ENV_ADDR-CFG_FLASH_BASE )

 

Where are the environment variables located now ?

If 0x20000000 is the emulated start of my SPI device, than 0x4000 is within the uboot-ldr section ?!?

 

I think 0x20000000 is the start adress for parallel flash.

Is that emulated when using SPI devices ???

 

The main problem: How to tell the jffs2 to use spi flash:

 

I defined

 

#define CFG_JFFS2_FIRST_BANK 0

#define CFG_JFFS2_NUM_BANKS 1

#define CFG_JFFS2_FIRST_SECTOR 8

 

so there is enough space ( 8x64kB = 512kB ) for the uboot at the beginning of the spi device-

 

Has there to be defined anything more ???

 

When i try fsinfo or ls, the system crahes after a while.

 

What is even unclear for me is the naming convention  ( sorry, Im german )

 

Does NAND Flash usually mean parallel organised flash

and NOR Flash serial organised flash ????

 

The documentation is a little bit confusing for me.

It is always spoken about flash. When i store the environment in the spi flash the configuration variable is no longer flash but EEPROM, what could also be an I2C device.

 

Could you please help me ?

 

Kind regards,

 

Marco

 

 

 

PS: I downloaded the latest toolchain and uboot from svn server. When compiling, uboot-ldr reports an error, that he doesnt know the command line option --bmode. Does the uboot-ldr anything modify on the ldr-file depending on the boot mode ?

 

I removed the --bmode option and than everything is bulding well.

 

Attached my configuration file:

 

--

 

/*

* U-boot - Configuration file for BF561 EZKIT board

*/

 

#ifndef __CONFIG_BF561_EZKIT_H__

#define __CONFIG_BF561_EZKIT_H__

 

#include <asm/blackfin-config-pre.h>

 

#define CONFIG_BFIN_CPU             bf561-0.3

//#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS

#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER

 

#define CONFIG_SPI

#define CONFIG_DEBUG_EARLY_SERIAL 1

 

#define CFG_LONGHELP        1

#define CONFIG_CMDLINE_EDITING    1

#define CONFIG_AUTO_COMPLETE    1

#define CONFIG_ENV_OVERWRITE    1

#define CONFIG_DEBUG_DUMP    1

#define CONFIG_DEBUG_DUMP_SYMS    1

#define CONFIG_BAUDRATE        57600

/* Set default serial console for bf537 */

#define CONFIG_UART_CONSOLE    0

 

 

#define CONFIG_PANIC_HANG 1

 

/*

* Board settings

*/

//#define CONFIG_DRIVER_SMC91111    1

#define CONFIG_SMC91111_BASE    0x2C010300

#define CONFIG_SMC_USE_32_BIT    1

 

/*

* Clock settings

*/

 

/* CONFIG_CLKIN_HZ is any value in Hz                */

#define CONFIG_CLKIN_HZ        30000000

/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN    */

/*                            1=CLKIN/2    */

#define CONFIG_CLKIN_HALF    0

/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass    */

/*                         1=bypass PLL    */

#define CONFIG_PLL_BYPASS    0

/* CONFIG_VCO_MULT controls what the multiplier of the PLL is    */

/* Values can range from 1-64                    */

#define CONFIG_VCO_MULT        20

/* CONFIG_CCLK_DIV controls what the core clock divider is    */

/* Values can be 1, 2, 4, or 8 ONLY                */

#define CONFIG_CCLK_DIV        1

/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */

/* Values can range from 1-15                    */

#define CONFIG_SCLK_DIV        6

/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider    */

/* Values can range from 2-65535                */

/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)            */

#define CONFIG_SPI_BAUD        2

#define CONFIG_SPI_BAUD_INITBLOCK    4

 

/*

* Network settings

*/

#if (CONFIG_DRIVER_SMC91111)

#define CONFIG_IPADDR        192.168.0.15

#define CONFIG_NETMASK        255.255.255.0

#define CONFIG_GATEWAYIP    192.168.0.1

#define CONFIG_SERVERIP        192.168.0.2

#define CONFIG_HOSTNAME        bf561-ezkit

#define CONFIG_ROOTPATH        /romfs

#endif                /* CONFIG_DRIVER_SMC91111 */

 

/*

* Flash settings

*/

 

#define CFG_FLASH_CFI        /* The flash is CFI compatible */

#define CFG_FLASH_CFI_DRIVER    /* Use common CFI driver */

#define CFG_FLASH_CFI_AMD_RESET

#define CFG_FLASH_BASE        0x20000000

#define CFG_MAX_FLASH_BANKS    1    /* max number of memory banks */

#define CFG_MAX_FLASH_SECT    40    /* max number of sectors on one chip */

/* JFFS Partition offset set  */

#define CFG_JFFS2_FIRST_BANK    0

#define CFG_JFFS2_NUM_BANKS    1

/* 512k reserved for u-boot */

#define CFG_JFFS2_FIRST_SECTOR    8

/* The BF561-EZKIT uses a top boot flash */

//#define    CFG_ENV_IS_IN_FLASH    1

#define    CFG_ENV_IS_IN_EEPROM    1

#define CFG_ENV_ADDR        0x20004000

#define CFG_ENV_OFFSET        (CFG_ENV_ADDR - CFG_FLASH_BASE)

#define CFG_ENV_SIZE        0x2000

#define    CFG_ENV_SECT_SIZE    0x10000    /* Total Size of Environment Sector */

#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)

#define ENV_IS_EMBEDDED

#else

#define ENV_IS_EMBEDDED_CUSTOM

#endif

 

/*

* SDRAM settings & memory map

*/

 

#define CONFIG_MEM_SIZE            32    /* 128, 64, 32, 16 */

#define    CFG_SDRAM_BASE        0x00000000

#define CFG_MAX_RAM_SIZE    (CONFIG_MEM_SIZE * 1024 * 1024)

 

#define CFG_MEMTEST_START    0x0    /* memtest works on */

#define CFG_MEMTEST_END        ( (CONFIG_MEM_SIZE - 1) * 1024*1024)    /* 1 ... 63 MB in DRAM */

 

#define CFG_LOAD_ADDR        CONFIG_LOADADDR

#define CFG_MONITOR_LEN        (256 << 10)    /* Reserve 256 kB for Monitor   */

#define CFG_MONITOR_BASE    (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)

#define CFG_MALLOC_LEN        (128 << 10)    /* Reserve 128 kB for malloc()  */

#define CFG_MALLOC_BASE        (CFG_MONITOR_BASE - CFG_MALLOC_LEN)

 

#define CFG_GBL_DATA_SIZE    0x4000

#define CFG_GBL_DATA_ADDR    (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)

#define CONFIG_STACKBASE    (CFG_GBL_DATA_ADDR  - 4)

#define CONFIG_STACKSIZE    (128*1024)    /* regular stack */

 

 

/*

* Command settings

*/

 

#define CFG_AUTOLOAD    "no"    /* rarpb, bootp, dhcp commands will    */

                /* only perform a configuration        */

                /* lookup from the BOOTP/DHCP server    */

                /* but not try to load any image    */

                /* using TFTP                */

 

#ifdef CONFIG_DRIVER_SMC91111

# define CONFIG_BFIN_CMD        (CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_DHCP)

#else

# define CONFIG_BFIN_CMD        (CONFIG_CMD_DFL & ~CFG_CMD_NET)

#endif

 

#define CONFIG_COMMANDS   \

    (CONFIG_BFIN_CMD    | \

     CFG_CMD_ELF        | \

     CFG_CMD_CACHE      | \

     CFG_CMD_JFFS2      | \

     CFG_CMD_DHCP)

 

/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */

#include <cmd_confdefs.h>

 

#define CONFIG_BFIN_COMMANDS \

    ( CFG_BFIN_CMD_CPLBINFO )

 

#define CONFIG_BOOTDELAY     5

#define CONFIG_BOOTCOMMAND   "run ramboot"

#define CONFIG_BOOTARGS      "root=/dev/mtdblock0 rw earlyprintk=serial,uart0," MK_STR(CONFIG_BAUDRATE)

#define CONFIG_LOADADDR      0x1000000

 

#if (CONFIG_COMMANDS & CFG_CMD_NET)

# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)

#  define UBOOT_ENV_FILE "u-boot.bin"

# else

#  define UBOOT_ENV_FILE "u-boot.ldr"

# endif

# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)

#  define UBOOT_ENV_UPDATE \

        "eeprom write $(loadaddr) 0x0 $(filesize)"

# else

#  define UBOOT_ENV_UPDATE \

        "protect off 0x20000000 0x2003FFFF;" \

        "erase 0x20000000 0x2003FFFF;" \

        "cp.b $(loadaddr) 0x20000000 $(filesize)"

# endif

# define NETWORK_ENV_SETTINGS \

    "ubootfile=" UBOOT_ENV_FILE "\0" \

    "update=" \

        "tftp $(loadaddr) $(ubootfile);" \

        UBOOT_ENV_UPDATE \

        "\0" \

    "addip=set bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):eth0:off\0" \

    "ramargs=set bootargs " CONFIG_BOOTARGS "\0" \

    "ramboot=" \

        "tftp $(loadaddr) uImage;" \

        "run ramargs;" \

        "run addip;" \

        "bootm" \

        "\0" \

    "nfsargs=set bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath),tcp,nfsvers=3\0" \

    "nfsboot=" \

        "tftp $(loadaddr) vmImage;" \

        "run nfsargs;" \

        "run addip;" \

        "bootm" \

        "\0"

#else

# define NETWORK_ENV_SETTINGS

#endif

#define CONFIG_EXTRA_ENV_SETTINGS \

    NETWORK_ENV_SETTINGS \

    "flashboot=bootm 0x20100000\0"

 

/*

* Console settings

*/

#define CFG_BAUDRATE_TABLE    { 9600, 19200, 38400, 57600, 115200 }

 

#define CFG_PROMPT "bfin> "

 

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)

#define    CFG_CBSIZE        1024        /* Console I/O Buffer Size */

#else

#define    CFG_CBSIZE        256        /* Console I/O Buffer Size */

#endif

#define    CFG_PBSIZE        (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)    /* Print Buffer Size */

#define    CFG_MAXARGS        16        /* max number of command args */

#define CFG_BARGSIZE        CFG_CBSIZE    /* Boot Argument Buffer Size */

 

#define CONFIG_LOADS_ECHO    1

 

/*

* Miscellaneous configurable options

*/

#define    CFG_HZ            1000        /* decrementer freq: 10 ms ticks */

#define CFG_BOOTM_LEN        0x4000000    /* Large Image Length, set to 64 Meg */

 

/*

* Soft I2C support

*/

//#define CONFIG_SOFT_I2C        1

#define PF_SCL            0x1/*PF0*/

#define PF_SDA            0x2/*PF1*/

 

#ifdef CONFIG_SOFT_I2C

#define I2C_INIT       do { *pFIO0_DIR |= PF_SCL; SSYNC(); } while (0)

#define I2C_ACTIVE     do { *pFIO0_DIR |= PF_SDA; *pFIO0_INEN &= ~PF_SDA; SSYNC(); } while (0)

#define I2C_TRISTATE   do { *pFIO0_DIR &= ~PF_SDA; *pFIO0_INEN |= PF_SDA; SSYNC(); } while (0)

#define I2C_READ       ((*pFIO0_FLAG_D & PF_SDA) != 0)

#define I2C_SDA(bit) \

    do { \

        if (bit) \

            *pFIO0_FLAG_S = PF_SDA; \

        else \

            *pFIO0_FLAG_C = PF_SDA; \

        SSYNC(); \

    } while (0)

#define I2C_SCL(bit) \

    do { \

        if (bit) \

            *pFIO0_FLAG_S = PF_SCL; \

        else \

            *pFIO0_FLAG_C = PF_SCL; \

        SSYNC(); \

    } while (0)

#define I2C_DELAY        udelay(5)    /* 1/4 I2C clock duration */

 

#define CFG_I2C_SPEED        50000

#define CFG_I2C_SLAVE        0

#endif

 

/*

* FLASH organization and environment definitions

*/

#define CONFIG_EBIU_SDRRC_VAL  0x306

#define CONFIG_EBIU_SDGCTL_VAL 0x91114d

#define CONFIG_EBIU_SDBCTL_VAL 0x15

//#define CONFIG_EBIU_SDBCTL_VAL 0x13

 

#define CONFIG_EBIU_AMGCTL_VAL        0x3F

#define CONFIG_EBIU_AMBCTL0_VAL        0x7BB07BB0

#define CONFIG_EBIU_AMBCTL1_VAL        0xFFC27BB0

 

#include <asm/blackfin-config-post.h>

 

#endif                /* __CONFIG_EZKIT561_H__ */

 

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2008-06-06 11:20:47     Re: uboot, jfss2 and environment on single spi-flash device

Mike Frysinger (UNITED STATES)

Message: 56819   

 

the top level README in the u-boot directory explains what the different defines are for

 

the u-boot jffs2 commands will not work with SPI flashes

 

parallel flash means directly addressable flash.  nand is not directly addressable, therefore it could not be parallel flash.  only nor flash can be directly addressable.

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2008-06-06 15:14:28     Re: uboot, jfss2 and environment on single spi-flash device

Marco Rohleder (GERMANY)

Message: 56826   

 

MIke, thank you for your reply.

 

Now i undertstand this.

 

But my problem is still not solved.

 

 

As mentioned before i now have the uboot at the first 512kByte of my SPI Flash Device.

I put the environment at the end of this 512KByte area.

I found out, that if ENV_IS_STORED_IN_EEPROM is defined and also CFG_SPI this is working well.

 

Because there are no other NV memories on board, i have although to put the linux kernel in this SPI Flash. There is space enough.

 

Is there a command to copy a certain amount of data from SPI flash to SDRAM ???

 

 

If so, i can copy the kernel out of SPI flash to SDRAM and after that, decompress and  boot it from there.

 

Or is this totally wrong and are there better ways to boot the complete linux kernel out of serial flash ?

 

I thought also about writing an expansion to that Nand staff to handle this with serial flash devices.

The only problem i found until now is, that as i saw in the source, the typical page size of a nand flash device is 512 Bytes while the spi flash can only be erased in blocks of 64k.

 

 

One solution could be to cache one 64k block and not to write it back until another 64k block is accessed.

That is only valid for write operations of course., since reading makes no problem.

 

What do you think about it ?

 

Have a nice weekend, Kind regards

 

Marco

 

 

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2008-06-06 15:55:09     Re: uboot, jfss2 and environment on single spi-flash device

Mike Frysinger (UNITED STATES)

Message: 56829   

 

the documentation explains how to work with SPI flash:

http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:serial-flash

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