2008-03-19 17:09:31     customizing u-boot

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2008-03-19 17:09:31     customizing u-boot

Ivan Koryakovskiy (RUSSIAN FEDERATION)

Message: 52777    Hi everybody!

 

Here are problems with which I have encountered during customizing 2008R1 u-boot. I used the following document: http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:porting.

CPU is 531-0.4

 

1) I boot from spi flash (M25P80) in slave mode and hence I use

 

#define BFIN_BOOT_SPI_SLAVE 4

 

But during compilation I had a problem with undefined CFG_MEMTEST_START. I defined it myself for BFIN_BOOT_SPI_SLAVE boot mode:

 

#define CFG_MEMTEST_START    0x00000000

 

But just would like to know what does this def means?

 

2) I need to make an ldr with PF2 flag set. How can I do this? I've seen this code, probably I need to change 6 to 2?

 

LDR_FLAGS-BFIN_BOOT_UART = --port g --gpio 6

LDR_FLAGS += $(LDR_FLAGS-$(BFIN_BOOT_MODE))

 

3) When I look at generated ldr in LdrViewer I see, that flag Resvect is set. But I have defined the following

 

#define CONFIG_BFIN_CPU             bf531-0.4

 

and in Booting Process.pdf:

 

Bit 1: RESVECT – Indicates the reset vector after booting. All ADSP-BF531/BF532/BF533

derivatives use the same Boot ROM. This bit is set to 0 for the ADSP-BF531/BF532 and it is set to

1 for the ADSP-BF533. After booting is complete, the on-chip Boot ROM uses this bit to jump to

address 0xFFA0 0000 for the ADSP-BF533 or to address 0xFFA0 8000 for the ADSPBF531/

BF532.

 

Maybe I need to define cpu somewhere else? (Nevertheless during compilation i see flag -mcpu=bf531-0.4 )

 

Thanks,

-Ivan

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2008-03-19 17:34:13     Re: customizing u-boot

Mike Frysinger (UNITED STATES)

Message: 52779    what do you mean you used "#define BFIN_BOOT_SPI_SLAVE 4" ?  there is no reason you need to create any BFIN_BOOT_* define.  plus, the boot mode reflects the view of the processor.  if you're booting out of SPI flash, the Blackfin processor is not the slave, it is the master.

 

CFG_MEMTEST_START should already be set to 0 for Blackfin boards ... if you want to know about memtest, read the toplevel README file in the u-boot source tree.

 

why do you think you need to set PF2 ?  it has no meaning in SPI master boot ... the BF533 family is hardcoded to CS2 and the bootrom takes care of that for you

 

as for the resvect issue, it's because ldr-utils does a case sensitive match against the target.  if you apply this change to your u-boot, it should work:

-               $(LDR) -T $(CONFIG_CPU) -f -c $@ $< $(LDR_FLAGS)

+               $(LDR) -T $(patsubst bf%,BF%,$(CONFIG_CPU)) -f -c $@ $< $(LDR_FLAGS)

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2008-03-19 17:57:01     Re: customizing u-boot

Ivan Koryakovskiy (RUSSIAN FEDERATION)

Message: 52780    Well, I found definisthon of BFIN_BOOT_SPI_SLAVE in u-boot-1.1.6/include/asm-blackfin/blackfin-config-pre.h file. I just used this definition in file u-boot-1.1.6/include/configs/bf531-x as

 

#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_SLAVE

 

But I am sorry, you are right - I have a master boot mode. So, I should use

 

#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER

 

I have a custom board, where PF2 is connected to ~CS input of flash. As much as I understand processor activates flash by pulling down this line. Actually I tried my small test programs without PF2 set (and they worked), but I think it's better do do everything in order.

 

about resvect - in which file should I put the code?

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2008-03-19 18:07:11     Re: customizing u-boot

Mike Frysinger (UNITED STATES)

Message: 52781    the bootrom documentation states that it only reads the pflag field in the case of SPI slave mode ... so using the flag is counter productive in that it makes you think it is actually respected.  you dont want to down the line think "oh we can just change the CS to CS3 since we need CS2 for something else and all have to do is change the software flag".

 

that diff was against the top level Makefile.  ive fixed ldr-utils to work properly in trunk, but i'll use that change for the branch so that people using older toolchain will get correct behavior.

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2008-03-19 18:18:58     Re: customizing u-boot

Ivan Koryakovskiy (RUSSIAN FEDERATION)

Message: 52782    Fine, resvect is reset

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2008-03-20 16:44:26     Re: customizing u-boot

Ivan Koryakovskiy (RUSSIAN FEDERATION)

Message: 52856    Hi!

I have some troubles while booting  u-boot. Actually  it doesn't  send anything via uart.

I found out in Booting Process.pdf that:

 

"The on-chip Boot ROM in silicon revision 0.3 checks whether the incoming data on the MISO

pin is anything other than 0xFF. For this reason, SPI loader files built for silicon revision 0.2 and

below must have the first byte as 0x00. For silicon revision 0.3, the first byte of the loader file is

set to 0x40."

 

While I have revision 0.4 and the first byte in ldr is 0x00. How can I fix it?

 

Nevertheless,I have changed initcode.c a bit to lit a led on my board in the very beginning. After powering i saw it lighting. So booting process is ok.

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2008-03-20 17:32:34     Re: customizing u-boot

Mike Frysinger (UNITED STATES)

Message: 52858    what is this "Booting Process.pdf" you refer to ?  ive never heard of it.

 

if the led blinked it means that the LDR is most likely fine.  if you dont have jtag to debug the situation, please review:

http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:debugging

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2008-03-20 17:39:32     Re: customizing u-boot

Ivan Koryakovskiy (RUSSIAN FEDERATION)

Message: 52859    Full name is EE-240 "ADSP-BF533 Blackfin® Booting Process"

 

Here is a link: http://www.analog.com/UploadedFiles/Application_Notes/44524304621268EE240v03.pdf

page 23

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2008-03-22 03:55:07     Re: customizing u-boot

Ivan Koryakovskiy (RUSSIAN FEDERATION)

Message: 52908    I have finally set it up. Here is what i did in initcode.c. probably it would be helpful.

 

1) moved writing to PLL_DIV and added SSYNC();

 

    //bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);

 

    serial_putc('K');

 

    /* Only reprogram when needed to avoid triggering unnecessary

     * PLL relock sequences.

     */

        if (bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {

        serial_putc('!');

        bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);

        SSYNC();

        asm("idle;");

    }

 

    bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);  

 

2) Added CONFIG_CLKIN_HALF in calculations (i'm using it) and commented SPORT_HYST (since i didn't find anything about what it is)

 

#ifndef CONFIG_PLL_CTL_VAL

# define CONFIG_PLL_CTL_VAL (/*SPORT_HYST |*/ (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF )

#endif

 

# define BFIN_CCLK (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV) >> CONFIG_CLKIN_HALF)

 

Thanks for help

-Ivan

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2008-03-22 07:07:47     Re: customizing u-boot

Mike Frysinger (UNITED STATES)

Message: 52916    the CLKIN_HALF missing from default PLL_CTL_VAL is obviously a bug as you've shown ... there should be no need for you to remove the SPORT_HYST bit as that should only affect the SPORT.  you'd have to read the anomaly list to find the explanation of that (it's only in newer parts so it isnt in the HRM yet).

 

however, the change of moving PLL_DIV after PLL_CTL should not be needed,nor the ssync.  can you check that only adding CLKIN_HALF fixes things and none of the other changes ?

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2008-03-23 05:06:58     Re: customizing u-boot

Ivan Koryakovskiy (RUSSIAN FEDERATION)

Message: 52934    Mike, I have checked it (with only CLKIN_HALF changes) and it works ok.

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2008-03-23 05:27:47     Re: customizing u-boot

Ivan Koryakovskiy (RUSSIAN FEDERATION)

Message: 52935    I also have such weird things:

 

bfin> version

 

U-Boot 1.1.6-svn1163 (ADI-2008R2-pre) (Mar 22 2008 - 22:01:34)

 

bfin>

 

U-Boot 1.1.6-svn1163 (ADI-2008R2-pre) (Mar 22 2008 - 22:01:34)

 

bfin>

 

When I write some commands (also date, erase) I see them executed twice.

While for others (md) output I see just once.

Is it a bug or what?

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2008-03-23 07:59:32     Re: customizing u-boot

Mike Frysinger (UNITED STATES)

Message: 52936    if you hit enter again, it'll re-run the last command automatically

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2008-03-26 06:02:45     Re: customizing u-boot

Ivan Koryakovskiy (RUSSIAN FEDERATION)

Message: 53044    I try to load vmImage now. But I have the following output either in HyperTerminal or in C-Kermit.

 

bfin> loadb 0x00400000

## Ready for binary (kermit) download to 0x00400000 at 57600 bps...

 

[SERIAL ERROR]

        DLL=0x6d DLH=0x0

          1: RBR=0x41 LSR=0x62

          0: RBR=0x01 LSR=0x60

 

[SERIAL ERROR]

        DLL=0x6d DLH=0x0

          0: RBR=0x0d LSR=0x62

 

with message like "no answer received".

 

With loady I have mostly the same output.

 

Here is some more information about board:

 

bfin> coninfo

List of available devices:

serial   80000003 SIO stdin stdout stderr

 

bfin> bdinfo

U-Boot      = U-Boot 1.1.6-svn1163 (ADI-2008R2-pre) (Mar 22 2008 - 22:01:34)

CPU         = bf531-0.4

Board       = bf531-sorex

VCO         = 400 MHz

CCLK        = 400 MHz

SCLK        = 100 MHz

boot_params = 0x00000000

memstart    = 0x00000000

memsize     = 0x01000000

flashstart  = 0x20000000

flashsize   = 0x00400000

flashoffset = 0x00000000

ethaddr     = 06:00:00:00:00:00

ip_addr     = 0.0.0.0

baudrate    = 57600 bps

bfin>

 

How can i fix it?

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2008-03-26 07:59:35     Re: customizing u-boot

Ivan Koryakovskiy (RUSSIAN FEDERATION)

Message: 53048    when I changed uart speed by

 

loadb 0x00400000 38400

 

everything went ok. it seems there is a problem with baudrate settings. maybe again because of CLKIN_HALF?

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2008-03-26 10:59:22     Re: customizing u-boot

Mike Frysinger (UNITED STATES)

Message: 53060    please try this patch:

http://blackfin.uclinux.org/git/?p=readonly-mirrors/u-boot.git;a=commitdiff;h=c94c3f08e099959773260db6130a8130805f8939

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2008-04-05 16:35:13     Re: customizing u-boot 1.1.6 for custom bf531 board

Kiril Petrov (BULGARIA)

Message: 53686    Hi Ivan,

 

several days I'm trying to build u-boot 1.1.6 for my custom bf531 board to boot from SPI, but without success (bf531-0.5, SPI flash M25P64VMF6, 64M SDRAM - MT48LC16M16A2-75). I read the whole thread, and make all correction mentioned here , but still no luck (Thanks to Mike Frysinger for solving resvect issue). After flashing my board via Jtag (IGLOO) on parallel port (spiflashmem 0 u-boot.ldr , is 0 correct address ?), and reset the board, all I get on serial console is

 

..........Шxаx.<.FIN>

 

Can you share your include/configs/<board>.h file, or at least compare with my <board>.h (attached), and point me to mistake if I made some.

bf531-ice.h

bf531-ice.h

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2008-04-06 07:24:39     Re: customizing u-boot 1.1.6 for custom bf531 board

Kiril Petrov (BULGARIA)

Message: 53704    When I building u-boot, the almost last command is:

 

bfin-uclinux-ldr -T BF531-0.5 -f -c u-boot.ldr u-boot --use-vmas --initcode cpu/blackfin/initcode.o --punchit $((0x4000)):$((0x2000)):env-ldr.o

Creating LDR u-boot.ldr ...

Adding DXE 'u-boot' ... [initcode 812] [jump block] [ELF block: 57664 @ 0x03FC0000] [ELF block: 36 @ 0xFFA0800C] [ELF block: 11348 @ 0x03FCE164] OK!

Done!

 

,and it is successfull. I've tryed this comamd without -f option, and again successfull, no matter that -T option doesn't support BF531-0.5 type of target, nearest is BF533 which support BF531 cpu. But when I've checked what bfin-uclinux-ldr auto detect, to my surprise it was BF537 ! What it's wrong ?

 

bfin-uclinux-ldr -s u-boot.ldr

Showing LDR u-boot.ldr ...

auto detected LDR as 'BF537'

  DXE 1 at 0x00000000:

    Block  1 at 0x00000000

         Addr: 0xFFA08000 Bytes: 0x0000032C Flags: 0x0008 ( init )

    Block  2 at 0x00000336

         Addr: 0xFFA08000 Bytes: 0x0000000C Flags: 0x0000 ( )

    Block  3 at 0x0000034C

         Addr: 0x03FC0000 Bytes: 0x00003CA0 Flags: 0x0000 ( )

    Block  4 at 0x00003FF6

         Addr: 0x00000000 Bytes: 0x00002000 Flags: 0x0010 ( ignore )

    Block  5 at 0x00006000

         Addr: 0x03FC3CA0 Bytes: 0x00004360 Flags: 0x0000 ( )

    Block  6 at 0x0000A36A

         Addr: 0x03FC8000 Bytes: 0x00006140 Flags: 0x0000 ( )

    Block  7 at 0x000104B4

         Addr: 0xFFA0800C Bytes: 0x00000024 Flags: 0x0000 ( )

    Block  8 at 0x000104E2

         Addr: 0x03FCE164 Bytes: 0x00002C54 Flags: 0x8001 ( zerofill final )

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2008-04-06 17:40:40     Re: customizing u-boot 1.1.6 for custom bf531 board

Mike Frysinger (UNITED STATES)

Message: 53710    the BF533/BF537 formats are the same

 

the -T option supports BF531-0.5 just fine, so i dont know what you're referring to

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2008-04-06 18:17:39     Re: customizing u-boot 1.1.6 for custom bf531 board

Kiril Petrov (BULGARIA)

Message: 53711    I've changed CONFIG_BFIN_CPU from bf531-0.5 to bf531-0.4 , and now I've a little shine BFIN> prompt . Durring booting, u-boot detect CPU as: CPU:    ADSP bf531-0.4 (Detected Rev: 0.5).  Is it safe to stay with bf531-0.4 , or I need to change/add something to work with bf531-0.5 ?

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2008-04-06 20:43:48     Re: customizing u-boot 1.1.6 for custom bf531 board

Mike Frysinger (UNITED STATES)

Message: 53713    0.5 silicon should work, but if it doesnt (and 0.4 does) implies issues with anomaly handling

 

i cant test BF533-0.5 on SPI boot, but i can test BF533-0.5 on parallel boot

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2008-04-18 20:13:14     Re: customizing u-boot 1.1.6 for custom bf531 board

Mike Frysinger (UNITED STATES)

Message: 54512    i only have a BF533-EZKIT with 0.5 silicon, but i'm able to configure/boot u-boot for bf531-0.5 silicon

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2008-04-21 16:17:59     Confirmed - u-boot 1.1.6, boot correctly on BF531-0.5

Kiril Petrov (BULGARIA)

Message: 54643    Hi Mike,

I've try it again with bf531-0.5 , and now it booting just fine,  via go 0x01000000, and after write to SPI eeprom and hit reset, it just works. I've try it even with my previous <board>.h (very early version) , attached in my previous post , and also works. So I think the problem is out of 1.1.6 , but in my very little experience with u-boot and JTAG tools, so I confirm once again that u-boot ver. 1.1.6 boot correctly on BF531 silicon revision 0.5

 

 

U-Boot 1.1.6-svn323 (ADI-2008R1) (Apr 21 2008 - 22:47:34)

 

CPU:   ADSP bf531-0.5 (Detected Rev: 0.5)

Board: BF531 ICE board

       Support: http://blackfin.uclinux.org/

Clock: VCO: 400 MHz, Core: 400 MHz, System: 133 MHz

RAM:   64 MB

In:    serial

Out:   serial

Err:   serial

Net:   DM9000#0

MAC:   02:80:AD:20:31:B8

...

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