2008-04-14 15:47:07     U-Boot/mDDR/SCLK issues

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2008-04-14 15:47:07     U-Boot/mDDR/SCLK issues

Kris Dickie (CANADA)

Message: 54209    Is the tracker item on the uclinux-dist for lowering the SCLK fixed or not? looks like sonicz has made some changes, but these only seem to affect the SDRAM timings. My u-boot code already takes the SCLK/DDR adjustments  into consideration, and I still can't get past initcode() when trying to run an 80 MHz SCLK, ie. i see SBLACKFIN> and that's all. I believe I will need to get to this level, as the anomaly existing for mDDR probably won't run properly at > 80 MHz on the existing silicon. mtest fails on 1/4 of addresses on a single pattern write and I am experiencing inconsistent bootups as shown below.

 

I'm still debugging, but thought I would throw this out to see if anyone can explain what could be happening.

I have a very stripped down u-boot, and environment is set to ENV_IS_NOWHERE, so basically the only thing that happens in env_relocate() is a memset() & memcpy(). I may have to do what Mike suggested in another thread on the uclinux-dist, which is do a mtest early on in initcode, since I am using mDDR at 130 MHz.

 

Anyways, here is my output with CCLK: 520: SCLK: 130, good and bad starts, maybe someone will have an idea.

 

Thanks

 

Good boot: happens about 7 out of 10 resets or power-ups.

 

SBLACKFIN>

Early:start.S: Init Registers

Early:start.S: Relocate

Early:start.S: Zero BSS

Early:start.S: Lower to 15

Early: NOP Slide

Early: Board init flash

Early: Init CPLB tables

Early: Exceptions setup

Early: Init global data

Early: IRQ init

Early: Environment init

Early: Baudrate init

Early: Serial init

Early: Console init flash

Early: End of early debugging

 

 

U-Boot 1.1.6-svn1182 (ADI-2008R1) (Apr 14 2008 - 11:53:08)

 

CPU:   ADSP bf548-0.0 (Detected Rev: 0.0)

Board: ADI BF54code       Support: http://blackfin.uclinux.org/

Hzock: VCO: 520 MHz, Core: 520 MHz, System: 130

RAM:   64 MB

Using default environment

 

In:    serial

Out:   serial

Err:   serial

gd: 3efc000

|-flags: 3

|-board_type: 0

|-baudrate: 57600

|-have_console: 1

|-ram_size: 0

|-reloc_off: 0

|-env_addr: 3f0000c

|-env_valid: 1

|-jt(3f02168): 3fa5c60

\-bd: 3efc028

   |-bi_baudrate: e100

   |   |-bi_enetaddr: 0 0 0 0 0 0

   |-bi_boot_params: 0

   |-bi_memstart: 0

   |-bi_memsize: 4000000

   |-bi_flashstart: 0

   |-bi_flashsize: 0

   \-bi_flashoffset: 0

bfin>

 

Bad boot: happens the rest of the time

 

SBLACKFIN>

Early:start.S: Init Registers

Early:start.S: Relocate

Early:start.S: Zero BSS

Early:start.S: Lower to 15

Early: NOP Slide

Early: Board init flash

Early: Init CPLB tables

Early: Exceptions setup

Early: Init global data

Early: IRQ init

Early: Environment init

Early: Baudrate init

Early: Serial init

Early: Console init flash

Early: End of early debugging

 

 

U-Boot 1.1.6-svn1182 (ADI-2008R1) (Apr 14 2008 - 11:53:08)

 

CPU:   ADSP bf548-0.0 (Detected Rev: 0.0)

Board: ADI BF54code       Support: http://blackfin.uclinux.org/

Hzock: VCO: 520 MHz, Core: 520 MHz, System: 130

RAM:   64 MB

Using default environme

 

 

Ack! Something bad happened to the Blackfin!

 

SEQUENCER STATUS:

SEQSTAT: 00002024  IPEND: 3fa0164  SYSCFG: 0032

  HWERRCAUSE: 0x0

  EXCAUSE   : 0x24

  physical IVG6 asserted : <0x03fa06d8> { _evt_default + 0x0 }

  physical IVG8 asserted : <0x03fa06d8> { _evt_default + 0x0 }

RETE: <0xdc851fe7> { ___smulsi3_highpart + 0xd88a7c43 }

RETN: <0x8fc7ca93> { ___smulsi3_highpart + 0x8bcd26ef }

RETX: <0x03fa5bee> { _env_relocate + 0x42 }

RETS: <0x03fa5be8> { _env_relocate + 0x3c }

PC  : <0x03fa0164> { _start + 0x164 }

DCPLB_FAULT_ADDR: <0x03facad4> { ___smulsi3_highpart + 0x2730 }

ICPLB_FAULT_ADDR: <0x03fa5bee> { _env_relocate + 0x42 }

 

PROCESSOR STATE:

R0 : 000000e0    R1 : 00000000    R2 : 00002000    R3 : 03fad298

R4 : 00000208    R5 : 07bfa480    R6 : 1efe9200    R7 : 03faf82c

P0 : 03fad298    P1 : 03f02008    P2 : ffc03114    P3 : 03efc000

P4 : 03facad7    P5 : 03efc000    FP : 03efbffc    SP : 03efbe88

LB0: 03fa0de0    LT0: 03fa0de0    LC0: 00000000

LB1: 03fa7496    LT1: 03fa7494    LC1: 00000000

B0 : dd03ba67    L0 : 00000000    M0 : cf60635e    I0 : 0000e100

B1 : d94fba9f    L1 : 00000000    M1 : 6de5ba4f    I1 : 03fad6ec

B2 : f5239d50    L2 : 00000000    M2 : 0d65e249    I2 : c365a510

B3 : 1d9f574b    L3 : 00000000    M3 : fd309e59    I3 : d9e9f91b

A0.w: 02080000   A0.x: 00000000   A1.w: 000031db   A1.x: 00000000

USP : ffb00ffc  ASTAT: 00000000

 

Hardware Trace:

   0 Target : <0x03fa0ba8> { _bfin_panic + 0x0 }

     Source : <0x03fa0d6c> { _trap_c + 0x188 }

   1 Target : <0x03fa0d62> { _trap_c + 0x17e }

     Source : <0x03fa0c00> { _trap_c + 0x1c }

   2 Target : <0x03fa0be4> { _trap_c + 0x0 }

     Source : <0x03fa067e> { _trap + 0x56 }

   3 Target : <0x03fa0628> { _trap + 0x0 }

     Source : <0x03fa5bea> { _env_relocate + 0x3e }

   4 Target : <0x03fa5be8> { _env_relocate + 0x3c }

     Source : <0x03fa0554> { _serial_putc + 0x48 }

   5 Target : <0x03fa0538> { _serial_putc + 0x2c }

     Source : <0x03fa0554> { _serial_putc + 0x48 }

   6 Target : <0x03fa0540> { _serial_putc + 0x34 }

     Source : <0x03fa054c> { _serial_putc + 0x40 }

   7 Target : <0x03fa0540> { _serial_putc + 0x34 }

     Source : <0x03fa054c> { _serial_putc + 0x40 }

   8 Target : <0x03fa0540> { _serial_putc + 0x34 }

     Source : <0x03fa054c> { _serial_putc + 0x40 }

   9 Target : <0x03fa0540> { _serial_putc + 0x34 }

     Source : <0x03fa054c> { _serial_putc + 0x40 }

  10 Target : <0x03fa0540> { _serial_putc + 0x34 }

     Source : <0x03fa054c> { _serial_putc + 0x40 }

  11 Target : <0x03fa0540> { _serial_putc + 0x34 }

     Source : <0x03fa054c> { _serial_putc + 0x40 }

  12 Target : <0x03fa0540> { _serial_putc + 0x34 }

     Source : <0x03fa054c> { _serial_putc + 0x40 }

  13 Target : <0x03fa0540> { _serial_putc + 0x34 }

     Source : <0x03fa054c> { _serial_putc + 0x40 }

  14 Target : <0x03fa0540> { _serial_putc + 0x34 }

     Source : <0x03fa054c> { _serial_putc + 0x40 }

  15 Target : <0x03fa0540> { _serial_putc + 0x34 }

     Source : <0x03fa054c> { _serial_putc + 0x40 }

 

Please reset the board

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2008-04-14 16:17:19     Re: U-Boot/mDDR/SCLK issues

Mike Frysinger (UNITED STATES)

Message: 54210    the tracker item you refer to is for the kernel only.  u-boot is not affected because you have to program the registers directly yourself.

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2008-04-14 17:11:19     Re: U-Boot/mDDR/SCLK issues

Kris Dickie (CANADA)

Message: 54213    ok thanks. does that mean that lower SCLK values now work in the kernel just via the DDR registers modification, the reporter seemed to try it out and still get the error. Is there more that needs to be done to run a lower SCLK? I have triple checked my u-boot register programming, and am still stuck running high clocks only.

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2008-04-14 18:24:15     Re: U-Boot/mDDR/SCLK issues

Kris Dickie (CANADA)

Message: 54219    Just talked to our field rep, looks like silicon rev 0.0 on the 548 won't  work with any DDR given anomaly 05000334, and there is no workaround available except not to use DDR for running instructions or storing data, so it looks like I will continue testing when we get some 0.1 boards.

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2008-04-14 18:32:54     Re: U-Boot/mDDR/SCLK issues

Mike Frysinger (UNITED STATES)

Message: 54220    that's generally how we tested things in the beginning.  the system would boot up most of the time and work.  if something crashed, we'd try again.  if it worked most of the time, it was probably a hardware bug.

 

once we got new boards, we scrapped all the old ones ;).

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