2008-04-07 17:00:40     u-boot board .h file

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2008-04-07 17:00:40     u-boot board .h file

blue hash (UNITED STATES)

Message: 53767    I'm trying to configure the SRAM(16Mb) for a custom BF537 board and get u-boot(1.1.6) to boot.

The board has two MT48LC8M8A2 chips (2Mb * 8 * 4 banks, 2 chips)


For my board configuration, I changed the following

#define CONFIG_MEM_SIZE            16    /* 128, 64, 32, 16 */

#define CONFIG_MEM_ADD_WDTH        10    /* 8, 9, 10, 11 */

#define CONFIG_MEM_MT48LC16M8A2TG_75    1


#define BFIN_BOOT_MODE       is at BFIN_BOOT_UART


In mem_init.h,

#if (CONFIG_MEM_MT48LC16M8A2TG_75)


    #define SDRAM_Tref      64    /* Refresh period in milliseconds   */

    #define SDRAM_NRA       4096    /* Number of row addresses in SDRAM */

    #define SDRAM_CL        CL_2



The address lines are connected to the SDRAM chips as below.

Whats SDRAM_CL, is it the number of chips. Why is it that some people

have success in getting u-boot to boot with the RTC off.







2008-04-07 18:28:23     Re: u-boot board .h file

Mike Frysinger (UNITED STATES)

Message: 53770    please consult the HRM for your processor.  those settings correspond to the EBIU_SDBCTL and EBIU_SDGCTL settings.


in this case, CL stands for CAS Latency.


wrt to RTC, i can only guess at what you're talking about.  some people do not disable the RTC pieces when their board does not actually have an RTC hooked up, so things may get hung up.




2008-04-08 10:56:41     Re: u-boot board .h file

blue hash (UNITED STATES)

Message: 53848    Thanks for the reply.

In mem_init.h



What is EBE. Is there a page on the wiki, documenting the SDRAM configs?




2008-04-08 11:10:40     Re: u-boot board .h file

Mike Frysinger (UNITED STATES)

Message: 53849    again, consult the HRM