What’s the function of the SYNC_CLK pin on the DDS?

Document created by DSB Employee on Sep 30, 2013
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A: What’s the function of the SYNC_CLK pin on the DDS?

 

Q: The SYNC_CLK pin is provided so the user can externally synchronize the IO_UPDATE signal and/or profile pin signals to the internal timing of the DDS core. For example, if the frequency tuning word is being continuously updated via SPI operations and consistent propagation time through the device is desired, then the IO_UPDATE must be sent synchronously to the SYNC_CLK. In addition, if multiple DDS devices are to be synchronized, a common IO_UPDATE to all parts must be synchronized to the master SYNC_CLK device.

If the IO_UPDATE signal on the IO_UPDATE pin is asynchronous to the SYNC_CLK, the pipe line delay through the device will incur an uncertainty of +/- one SYNC_CLK period.  Note, the minimum pulse width of IO_UPDATE signal must be at least one SYNC_CLK period to be registered.

If more than one profile pin is switched at a time, the profile signals are required to be synchronized to the SYNC_CLK. If not, the correct internal profile register may or may not be chosen. However, if only one profile pin is switched at a time, the profile signal can be sent asynchronous to the SYNC_CLK, but the same pipe line delay uncertainty of +/- one SYNC_CLK period will exist.

Note in most DDS products, if the profile signals are sent asynchronous to the SYNC_CLK and the wrong profile is selected, issuing an IO_UPDATE can force the correct profile setting. However, the output would have been at the wrong profile setting until the correct profile setting is forced.

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