FAQ: [#6683] spi_bfin5xx: GPIO controlled SSEL deasserted too early(2011)

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[#6683] spi_bfin5xx: GPIO controlled SSEL deasserted too early

Submitted By: Mike Frysinger

Open Date

2011-07-07 16:39:50    

Priority:

Medium     Assignee:

Sonic Zhang

Status:

Open     Fixed In Release:

N/A

Found In Release:

2010R1-RC5     Release:

Category:

N/A     Board:

N/A

Processor:

ALL     Silicon Revision:

Is this bug repeatable?:

Yes     Resolution:

Fixed

Uboot version or rev.:

    Toolchain version or rev.:

trunk

App binary format:

N/A     

Summary: spi_bfin5xx: GPIO controlled SSEL deasserted too early

Details:

 

as reported here:

http://blackfin.uclinux.org/gf/forumthread/44481

 

it seems the logic in our SPI bus master deasserts the SPI GPIO CS before the data has finished transferring

 

Follow-ups

 

--- Sonic Zhang                                              2011-08-11 06:56:57

Fixed.

Poll the FIFO till it is empty before deasserting SSEL in pump_transfers in

soft irq mode. No polling is necessary in interrupt mode and error handling.

 

 

 

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