FAQ:[#6431] bfin-dma test can not execute in bf561-ezkit(2010)

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[#6431] bfin-dma test can not execute in bf561-ezkit

Submitted By: Vivi Li

Open Date

2010-12-30 22:14:39     Close Date

2011-01-18 22:58:17

Priority:

Medium     Assignee:

steven miao

Status:

Closed     Fixed In Release:

N/A

Found In Release:

2011R1     Release:

Category:

Tests     Board:

N/A

Processor:

BF561     Silicon Revision:

Is this bug repeatable?:

Yes     Resolution:

Fixed

Uboot version or rev.:

    Toolchain version or rev.:

gcc4.3-2010_Dec_09

App binary format:

N/A     

Summary: bfin-dma test can not execute in bf561-ezkit

Details:

 

bfin-dma test can not execute to the end in bf561-ezkit in latest trunk.

 

Last passed time is before 2010r1 release:

--

kernel:    Linux release 2.6.34.7-ADI-2010R1-pre-svn9171, build #72 Wed Sep 29 17:10:35 GMT 2010

toolchain: bfin-uclinux-gcc release gcc version 4.3.5 (ADI-trunk/svn-4747)

user-dist: release svn-9833, build #1167 Wed Sep 29 17:09:58 GMT 2010

--

 

--

Linux version 2.6.36.2-ADI-2011R1-pre-svn9539 (test@linux66-561-jtag-capture) (gcc version 4.3.5 (ADI-trunk/svn-5013) ) #4 Thu D0

register early platform devices

bootconsole [early_shadow0] enabled

bootconsole [early_BFuart0] enabled

early printk enabled on early_BFuart0

Board Memory: 64MB

Kernel Managed Memory: 64MB

Memory map:

  fixedcode = 0x00000400-0x00000490

  text      = 0x00001000-0x00103cf8

  rodata    = 0x00103cf8-0x001570dc

  bss       = 0x00158000-0x00168788

  data      = 0x00168788-0x0017a000

    stack   = 0x00178000-0x0017a000

  init      = 0x0017a000-0x00713000

  available = 0x00713000-0x03f00000

  DMA Zone  = 0x03f00000-0x04000000

Hardware Trace Active and Enabled

Boot Mode: 0

Blackfin support (C) 2004-2010 Analog Devices, Inc.

Compiled for ADSP-BF561 Rev 0.5

Blackfin Linux support by http://blackfin.uclinux.org/

Processor Speed: 600 MHz core clock and 100 MHz System Clock

NOMPU: setting up cplb tables

Instruction Cache Enabled for CPU0

  External memory: cacheable in instruction cache

  L2 SRAM        : uncacheable in instruction cache

Data Cache Enabled for CPU0

  External memory: cacheable (write-back) in data cache

  L2 SRAM        : cacheable (write-through) in data cache

Built 1 zonelists in Zone order, mobility grouping off.  Total pages: 16002

Kernel command line: root=/dev/mtdblock0 rw clkin_hz=30000000 earlyprintk=serial,uart0,57600 console=ttyBF0,57600 ip=10.100.4.50f

PID hash table entries: 256 (order: -2, 1024 bytes)

Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)

Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)

Memory available: 56700k/65536k RAM, (5732k init code, 1035k kernel code, 473k data, 1024k dma, 572k reserved)

Hierarchical RCU implementation.

        RCU-based detection of stalled CPUs is disabled.

        Verbose stalled-CPUs detection is disabled.

NR_IRQS:153

Configuring Blackfin Priority Driven Interrupts

console [ttyBF0] enabled, bootconsole disabled

console [ttyBF0] enabled, bootconsole disabled

Calibrating delay loop... 1196.03 BogoMIPS (lpj=2392064)

pid_max: default: 32768 minimum: 301

Mount-cache hash table entries: 512

Blackfin Scratchpad data SRAM: 4 KB

Blackfin L1 Data A SRAM: 16 KB (16 KB free)

Blackfin L1 Data B SRAM: 16 KB (16 KB free)

Blackfin L1 Instruction SRAM: 16 KB (3 KB free)

Blackfin L2 SRAM: 128 KB (128 KB free)

NET: Registered protocol family 16

Blackfin DMA Controller

ezkit_init(): registering device resources

bio: create slab <bio-0> at 0

bfin-spi bfin-spi.0: Blackfin on-chip SPI Controller Driver, Version 1.0, regs_base@ffc00500, dma channel@16

Switching to clocksource bfin_cs_cycles

NET: Registered protocol family 2

IP route cache hash table entries: 1024 (order: 0, 4096 bytes)

TCP established hash table entries: 2048 (order: 2, 16384 bytes)

TCP bind hash table entries: 2048 (order: 1, 8192 bytes)

TCP: Hash tables configured (established 2048 bind 2048)

TCP reno registered

UDP hash table entries: 256 (order: 0, 4096 bytes)

UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)

NET: Registered protocol family 1

debug-mmrs: setting up Blackfin MMR debugfs

msgmni has been set to 110

io scheduler noop registered (default)

bfin-dma: initialized

bfin-uart: Blackfin serial driver

bfin-uart.0: ttyBF0 at MMIO 0xffc00400 (irq = 35) is a BFIN-UART

brd: module loaded

smc91x.c: v1.1, sep 22 2004 by Nicolas Pitre <nico@fluxnic.net>

eth0: SMC91C11xFD (rev 1) at 2c010300 IRQ 82 [nowait]

eth0: Ethernet addr: 00:e0:22:fe:b1:3c

bfin-wdt: initialized: timeout=20 sec (nowayout=0)

TCP cubic registered

NET: Registered protocol family 17

eth0: link down

IP-Config: Complete:

     device=eth0, addr=10.100.4.50, mask=255.255.255.0, gw=10.100.4.174,

     host=bf561-ezkit, domain=, nis-domain=(none),

     bootserver=10.100.4.174, rootserver=10.100.4.174, rootpath=

dma_alloc_init: dma_page @ 0x02772000 - 256 pages at 0x03f00000

Freeing unused kernel memory: 5732k freed

                           _____________________________________

        a8888b.           / Welcomeeto the hCli0ux :ist ibulioni\

n   k  d 888u8b.p   ,    /  1   0_  0  _M   b   p   s   ,       f\

x   4   1|o|Eo|81   u   p   l   e | x |_,       l   p__ a__  TM)0 |

___/        | |    _ ____  _   _ \ \/ /       |

       8'    .88       \        | |   | |  _ \| | | | \  /        |

       8`._.' Y8.       \       | |__ | | | | | |_| | /  \        |

      d/      `8b.       \      \____||_|_| |_|\____|/_/\_\       |

     dP   .    Y8b.       \   For embedded processors including   |

    d8:'  "  `::88b        \    the Analog Devices Blackfin      /

   d8"         'Y88b        \___________________________________/

  :8P    '      :888

   8a.   :     _a88P         For further information, check out:

._/"Yaa_:   .| 88P|            - http://blackfin.uclinux.org/

\    YP"    `| 8P  `.          - http://docs.blackfin.uclinux.org/

/     \.___.d|    .'           - http://www.uclinux.org/

`--..__)8888P`._.'  jgs/a:f    - http://www.analog.com/blackfin

 

Have a lot of fun...

 

 

BusyBox v1.18.1 (2010-12-30 17:28:53 CST) hush - the humble shell

 

root:/> version

kernel:    Linux release 2.6.36.2-ADI-2011R1-pre-svn9539, build #4 Thu Dec 30 23:58:14 CST 2010

toolchain: bfin-uclinux-gcc release gcc version 4.3.5 (ADI-trunk/svn-5013)

user-dist: release svn-10026, build #31 Thu Dec 30 23:57:28 CST 2010

root:/> bfin-dma

open(/dev/bfin-dma) = 3

ioctl(3, 1076642816: BF_DMA_REQUEST, 0x28bbec4) = 0

ioctl(3, 1076642818: BF_DMA_RUN, 0x28bbec4) =

 

--

 

Follow-ups

 

--- steven miao                                              2011-01-11 04:21:52

MDMA io base defined in arch/blackfin/mach-bf561/dma.c do not match the

definition

of MDMA MMRs in arch/blackfin/mach-bf561/include/mach/defBF561.h

 

--- Mike Frysinger                                           2011-01-11 15:52:00

this shouldnt matter.  i purposefully changed the MMR names to make the BF561

match all the other Blackfin parts.  the bfin-dma driver should work with any of

the 4 MDMA streams.  so this bug implies that it is only working with one of

them rather than all 4.

 

--- steven miao                                              2011-01-11 22:46:38

you standardized BF561 MMR names in commit r9395, but in

arch/blackfin/mach-bf561/dma.c MDMA_S0-S4 MDMA_D0-D4 could not match the

register address you defined in defBF561.h, it caused we use the wrong MDMA

channel registers.

it should not matter with bfin-dma driver.

 

--- Mike Frysinger                                           2011-01-12 01:16:16

i dont know what you mean.  the order of addresses in dma_io_base_addr[] doesnt

matter.  the array is indexed by the CH_MEM_STREAM* defines.  and even then, the

only thing that matters is that an individual source and dest pair match.  we

could call 0xFFC00F08 D0, or D1, or D12391241 as long as 0xFFC00F48 is paired up

alongside it.

 

so the MMR addresses should retain their new names (before rev 9559), and if

there is a src/dst mismatch in dma.c or CH_MEM_*, then we should fix that.

 

--- steven miao                                              2011-01-12 22:00:57

the order in dma_io_base_addr[] should match with CH_MEM_* and the register

address. for example, CH_MEM_STREAM0_DEST match MDMA_D0_NEXT_DESC_PTR in

dma_io_base_addr[] and IRQ_MEM_DMA0 in channel2irq, so it should paired up with

0xFFC01F00. whatever you can rename it to D1,D2 or Dx, the channel should match

the IRQ and the register address. so we should define 0xFFC01F00 as MDMA_D0.

 

--- Vivi Li                                                  2011-01-17 02:33:27

Test can pass in regression.

If there is no objection, I will close this bug.

 

--- Vivi Li                                                  2011-01-18 22:58:17

Close it.

 

 

 

    Files

    Changes

    Commits

    Dependencies

    Duplicates

    Associations

    Tags

 

File Name     File Type     File Size     Posted By

config.linux.bfindma    application/octet-stream    30956    Vivi Li

config.config.bfindma    application/octet-stream    51526    Vivi Li

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