[#5833] trap test running on the second core of bf561 has serveral fails

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[#5833] trap test running on the second core of bf561 has serveral fails

Submitted By: Mingquan Pan

Open Date

2010-01-18 22:17:54     Close Date

2010-03-26 04:14:22

Priority:

Medium     Assignee:

Graf Yang

Status:

Closed     Fixed In Release:

N/A

Found In Release:

2010R1     Release:

Category:

N/A     Board:

N/A

Processor:

BF561     Silicon Revision:

Is this bug repeatable?:

Yes     Resolution:

Fixed

Uboot version or rev.:

    Toolchain version or rev.:

ADI-trunk/svn-3771

App binary format:

N/A     

Summary: trap test running on the second core of bf561 has serveral fails

Details:

 

trap test running on the second core of bf561 has serveral fails.

 

uname -a^M

Linux blackfin 2.6.32.3-ADI-2010R1-pre-svn8173 #24 SMP Mon Jan 18 06:37:42 GMT 2010 blackfin GNU/Linux^M

root:/>

 

taskset 2 ./traps_test -1

 

Running test 0 for exception 0x00: flush scratch pad

... FAIL (test failed, but not with the right signal)

        (We expected 0 'Unknown signal 0' but instead we got 7 'Bus error')

FAIL (test completed properly 0/1 times)

 

Running test 1 for exception 0x00: l1_dataA

... FAIL (test failed, but not with the right signal)

        (We expected 0 'Unknown signal 0' but instead we got 7 'Bus error')

FAIL (test completed properly 0/1 times)

 

Running test 2 for exception 0x00: l1_dataB

... FAIL (test failed, but not with the right signal)

        (We expected 0 'Unknown signal 0' but instead we got 7 'Bus error')

FAIL (test completed properly 0/1 times)

 

Running test 3 for exception 0x00: l1_instruction

... FAIL (test failed, but not with the right signal)

        (We expected 0 'Unknown signal 0' but instead we got 7 'Bus error')

FAIL (test completed properly 0/1 times)

 

Running test 4 for exception 0x00: flush_l1_non

... FAIL (test failed, but not with the right signal)

        (We expected 0 'Unknown signal 0' but instead we got 7 'Bus error')

FAIL (test completed properly 0/1 times)

 

Running test 5 for exception 0x00: flush_sysmmr

... PASS (test completed 1/1 times, as expected by signal 0: Unknown signal 0)

 

Running test 6 for exception 0x00: flush_coremmr

... PASS (test completed 1/1 times, as expected by signal 0: Unknown signal 0)

 

Running test 7 for exception 0x00: iflush null pointer

... PASS (test completed 1/1 times, as expected by signal 0: Unknown signal 0)

 

Running test 8 for exception 0x00: iflush unpopulated address

... PASS (test completed 1/1 times, as expected by signal 0: Unknown signal 0)

 

Running test 9 for exception 0x00: iflush unpopulated odd address

... PASS (test completed 1/1 times, as expected by signal 0: Unknown signal 0)

 

Running test 10 for exception 0x00: iflush scratch pad

... PASS (test completed 1/1 times, as expected by signal 0: Unknown signal 0)

 

Running test 11 for exception 0x00: iflush l1_dataA

... PASS (test completed 1/1 times, as expected by signal 0: Unknown signal 0)

 

Running test 12 for exception 0x00: iflush l1_dataB

... PASS (test completed 1/1 times, as expected by signal 0: Unknown signal 0)

 

Running test 13 for exception 0x00: iflush l1_instruction

... PASS (test completed 1/1 times, as expected by signal 0: Unknown signal 0)

 

Running test 14 for exception 0x00: iflush_l1_non

... PASS (test completed 1/1 times, as expected by signal 0: Unknown signal 0)

 

Running test 15 for exception 0x00: iflush_sysmmr

... PASS (test completed 1/1 times, as expected by signal 0: Unknown signal 0)

 

Running test 16 for exception 0x00: iflush_coremmr

... PASS (test completed 1/1 times, as expected by signal 0: Unknown signal 0)

 

Running test 17 for exception 0x00: flushinv scratch pad

... FAIL (test failed, but not with the right signal)

        (We expected 0 'Unknown signal 0' but instead we got 7 'Bus error')

FAIL (test completed properly 0/1 times)

 

Running test 18 for exception 0x00: flushinv l1_dataA

... FAIL (test failed, but not with the right signal)

        (We expected 0 'Unknown signal 0' but instead we got 7 'Bus error')

FAIL (test completed properly 0/1 times)

 

Running test 19 for exception 0x00: flushinv l1_dataB

... FAIL (test failed, but not with the right signal)

        (We expected 0 'Unknown signal 0' but instead we got 7 'Bus error')

FAIL (test completed properly 0/1 times)

 

Running test 20 for exception 0x00: flushinv l1_instruction

... FAIL (test failed, but not with the right signal)

        (We expected 0 'Unknown signal 0' but instead we got 7 'Bus error')

FAIL (test completed properly 0/1 times)

 

Running test 21 for exception 0x00: flushinv _l1_non

... FAIL (test failed, but not with the right signal)

        (We expected 0 'Unknown signal 0' but instead we got 7 'Bus error')

FAIL (test completed properly 0/1 times)

 

Running test 22 for exception 0x00: flushinv _sysmmr

... PASS (test completed 1/1 times, as expected by signal 0: Unknown signal 0)

 

Running test 23 for exception 0x00: flushinv _coremmr

... PASS (test completed 1/1 times, as expected by signal 0: Unknown signal 0)

 

Running test 24 for exception 0x01: EXCPT 0x01

... PASS (test completed 1/1 times, as expected by signal 5: Trace/breakpoint trap)

 

Running test 25 for exception 0x02: EXCPT 0x02

... PASS (test completed 1/1 times, as expected by signal 4: Illegal instruction)

 

Running test 26 for exception 0x03: EXCPT 0x03

... PASS (test completed 1/1 times, as expected by signal 11: Segmentation fault)

 

Running test 27 for exception 0x04: EXCPT 0x04

... PASS (test completed 1/1 times, as expected by signal 4: Illegal instruction)

 

Running test 28 for exception 0x05: EXCPT 0x05

... PASS (test completed 1/1 times, as expected by signal 4: Illegal instruction)

 

Running test 29 for exception 0x06: EXCPT 0x06

... PASS (test completed 1/1 times, as expected by signal 4: Illegal instruction)

 

Running test 30 for exception 0x07: EXCPT 0x07

... PASS (test completed 1/1 times, as expected by signal 4: Illegal instruction)

 

Running test 31 for exception 0x08: EXCPT 0x08

... PASS (test completed 1/1 times, as expected by signal 4: Illegal instruction)

 

Running test 32 for exception 0x09: EXCPT 0x09

... PASS (test completed 1/1 times, as expected by signal 4: Illegal instruction)

 

Running test 33 for exception 0x0a: EXCPT 0x0A

... PASS (test completed 1/1 times, as expected by signal 4: Illegal instruction)

 

Running test 34 for exception 0x0b: EXCPT 0x0B

... PASS (test completed 1/1 times, as expected by signal 4: Illegal instruction)

 

Running test 35 for exception 0x0c: EXCPT 0x0C

... PASS (test completed 1/1 times, as expected by signal 4: Illegal instruction)

 

Running test 36 for exception 0x0d: EXCPT 0x0D

... PASS (test completed 1/1 times, as expected by signal 4: Illegal instruction)

 

Running test 37 for exception 0x0e: EXCPT 0x0E

... PASS (test completed 1/1 times, as expected by signal 4: Illegal instruction)

 

Running test 38 for exception 0x0f: EXCPT 0x0F

... PASS (test completed 1/1 times, as expected by signal 4: Illegal instruction)

 

Running test 39 for exception 0x21: Invalid Opcode

... PASS (test completed 1/1 times, as expected by signal 4: Illegal instruction)

 

Running test 40 for exception 0x22: Illegal Instruction

... PASS (test completed 1/1 times, as expected by signal 4: Illegal instruction)

 

Running test 41 for exception 0x23: Illegal use of supervisor resource - MMR Read

... PASS (test completed 1/1 times, as expected by signal 11: Segmentation fault)

 

Running test 42 for exception 0x23: Illegal use of supervisor resource - MMR Write

... PASS (test completed 1/1 times, as expected by signal 11: Segmentation fault)

 

Running test 43 for exception 0x24: Data read misaligned address violation

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

 

Running test 44 for exception 0x24: Data write misaligned address violation

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

 

Running test 45 for exception 0x24: Stack set to odd address - misaligned address violation

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

 

Running test 46 for exception 0x24: Stack push to odd address

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

 

Running test 47 for exception 0x26: Data Read CPLB miss

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

 

Running test 48 for exception 0x26: Data Write CPLB miss

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

 

Running test 49 for exception 0x26: Stack CPLB miss

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

 

Running test 50 for exception 0x26: Stack push to miss

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

 

Running test 51 for exception 0x26: flush unpopulated address

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

 

Running test 52 for exception 0x26: flush unpopulated odd address

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

 

Running test 53 for exception 0x26: prefetch unpopulated address

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

 

Running test 54 for exception 0x26: prefetch unpopulated odd address

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

 

Running test 55 for exception 0x26: flushinv unpopulated address

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

 

Running test 56 for exception 0x26: flushinv unpopulated odd address

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

 

Running test 57 for exception 0x27: Data access multiple CPLB hits/Null Pointer Read

... PASS (test completed 1/1 times, as expected by signal 11: Segmentation fault)

 

Running test 58 for exception 0x27: Data access multiple CPLB hits/Null Pointer Write

... PASS (test completed 1/1 times, as expected by signal 11: Segmentation fault)

 

Running test 59 for exception 0x27: Stack set to zero

... PASS (test completed 1/1 times, as expected by signal 11: Segmentation fault)

 

Running test 60 for exception 0x27: Stack, push while SP is zero

... PASS (test completed 1/1 times, as expected by signal 11: Segmentation fault)

 

Running test 61 for exception 0x27: flush null pointer

... PASS (test completed 1/1 times, as expected by signal 11: Segmentation fault)

 

Running test 62 for exception 0x27: prefetch null pointer

... PASS (test completed 1/1 times, as expected by signal 11: Segmentation fault)

 

Running test 63 for exception 0x27: flushinv null pointer

... PASS (test completed 1/1 times, as expected by signal 11: Segmentation fault)

 

Running test 64 for exception 0x2a: Instruction fetch misaligned address violation

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

 

Running test 65 for exception 0x2b: Jump to L1 Data A

... FAIL (test failed with wrong EXCAUSE, expected 2b, but got 2c)

FAIL (test failed with wrong EXCAUSE, expected 0x2b, but got 0x2c)

FAIL (test completed properly 0/1 times)

 

Running test 66 for exception 0x2b: Return to L1 Data A

... FAIL (test failed with wrong EXCAUSE, expected 2b, but got 2c)

FAIL (test failed with wrong EXCAUSE, expected 0x2b, but got 0x2c)

FAIL (test completed properly 0/1 times)

 

Running test 67 for exception 0x2b: Jump to L1 Data B

... FAIL (test failed with wrong EXCAUSE, expected 2b, but got 2c)

FAIL (test failed with wrong EXCAUSE, expected 0x2b, but got 0x2c)

FAIL (test completed properly 0/1 times)

 

Running test 68 for exception 0x2b: Return to L1 Data B

... FAIL (test failed with wrong EXCAUSE, expected 2b, but got 2c)

FAIL (test failed with wrong EXCAUSE, expected 0x2b, but got 0x2c)

FAIL (test completed properly 0/1 times)

 

Running test 69 for exception 0x2b: Jump to L1 scratchpad

... FAIL (test failed with wrong EXCAUSE, expected 2b, but got 2c)

FAIL (test failed with wrong EXCAUSE, expected 0x2b, but got 0x2c)

FAIL (test completed properly 0/1 times)

 

Running test 70 for exception 0x2b: Return to scratchpad

... FAIL (test failed with wrong EXCAUSE, expected 2b, but got 2c)

FAIL (test failed with wrong EXCAUSE, expected 0x2b, but got 0x2c)

FAIL (test completed properly 0/1 times)

 

Running test 71 for exception 0x2c: Instruction fetch CPLB miss

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

 

Running test 72 for exception 0x2c: Jump to MMR Space

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

 

Running test 73 for exception 0x2c: Return to non-existant L3

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

 

Running test 74 for exception 0x2c: Return to an MMR address

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

 

Running test 75 for exception 0x2d: Instruction fetch multiple CPLB hits - Jump to zero

... PASS (test completed 1/1 times, as expected by signal 11: Segmentation fault)

 

Running test 76 for exception 0x2d: Return to zero

... PASS (test completed 1/1 times, as expected by signal 11: Segmentation fault)

 

Running test 77 for exception 0x2e: Illegal use of supervisor resource - Instruction

... PASS (test completed 1/1 times, as expected by signal 4: Illegal instruction)

 

Running test 78 for exception 0x3f: Read of L1 instruction

... FAIL (test failed with wrong EXCAUSE, expected 3f, but got 26)

FAIL (test failed with wrong EXCAUSE, expected 0x3f, but got 0x26)

FAIL (test completed properly 0/1 times)

 

Running test 79 for exception 0x3f: Write of L1 instruction

... FAIL (test failed with wrong EXCAUSE, expected 3f, but got 26)

FAIL (test failed with wrong EXCAUSE, expected 0x3f, but got 0x26)

FAIL (test completed properly 0/1 times)

 

Running test 80 for exception 0x3f: Jump to non-existant L1

... FAIL (test failed with wrong EXCAUSE, expected 3f, but got 2c)

FAIL (test failed with wrong EXCAUSE, expected 0x3f, but got 0x2c)

FAIL (test completed properly 0/1 times)

 

Running test 81 for exception 0x3f: Read non-existant L1

... FAIL (test failed with wrong EXCAUSE, expected 3f, but got 26)

FAIL (test failed with wrong EXCAUSE, expected 0x3f, but got 0x26)

FAIL (test completed properly 0/1 times)

 

Running test 82 for exception 0x3f: Write non-existant L1

... FAIL (test failed with wrong EXCAUSE, expected 3f, but got 26)

FAIL (test failed with wrong EXCAUSE, expected 0x3f, but got 0x26)

FAIL (test completed properly 0/1 times)

 

Running test 83 for exception 0x3f: Write non-existant L1, then system call

... FAIL (test failed with wrong EXCAUSE, expected 3f, but got 26)

FAIL (test failed with wrong EXCAUSE, expected 0x3f, but got 0x26)

FAIL (test completed properly 0/1 times)

 

Running test 84 for exception 0x3f: Return to non-existant L1

... FAIL (test failed with wrong EXCAUSE, expected 3f, but got 2c)

FAIL (test failed with wrong EXCAUSE, expected 0x3f, but got 0x2c)

FAIL (test completed properly 0/1 times)

 

Running test 85 for exception 0x3f: Stack set to L1 instruction

... FAIL (test failed with wrong EXCAUSE, expected 3f, but got 26)

FAIL (test failed with wrong EXCAUSE, expected 0x3f, but got 0x26)

FAIL (test completed properly 0/1 times)

 

Running test 86 for exception 0x3f: Stack set to non-existant L1

... FAIL (test failed with wrong EXCAUSE, expected 3f, but got 26)

FAIL (test failed with wrong EXCAUSE, expected 0x3f, but got 0x26)

FAIL (test completed properly 0/1 times)

 

Running test 87 for exception 0x3f: Stack push to non-existant L1

... FAIL (test failed with wrong EXCAUSE, expected 3f, but got 26)

FAIL (test failed with wrong EXCAUSE, expected 0x3f, but got 0x26)

FAIL (test completed properly 0/1 times)

 

62/88 tests passed

root:/bin>

 

Follow-ups

 

--- Mike Frysinger                                           2010-01-18 23:09:08

the trap test was written expecting to only be run on core 1.  it'll be good to

get it fixed to detect the core it is on and adjust memory mappings at runtime.

 

--- Graf Yang                                                2010-03-22 05:18:39

Done

 

--- Mingquan Pan                                             2010-03-26 04:13:03

It can work on either core 1 or core 2 now.

 

root:/> version^M

kernel:    Linux release 2.6.33.1-ADI-2010R1-pre-svn8546, build #4 SMP Fri Mar

26 00:39:55 GMT 2010^M

toolchain: bfin-uclinux-gcc release gcc version 4.3.4 (ADI-trunk/svn-3815) ^M

user-dist: release svn-9530, build #36 Fri Mar 26 00:38:36 GMT 2010^M

root:/> successful boot attempt

************** STEP 3: Start testing.

 

uname -a^M

Linux blackfin 2.6.33.1-ADI-2010R1-pre-svn8546 #4 SMP Fri Mar 26 00:39:55 GMT

2010 blackfin GNU/Linux^M

root:/>

It's a SMP kernel!

cd /bin^M

root:/bin> ./traps_test #^M

87^M

root:/bin> Total case num is 88.

taskset 1 ./traps_test -1^M

^M

Running test 0 for exception 0x00: flush scratch pad^M

... PASS (test completed 1/1 times, as expected by signal 0: Unknown signal

0)^M

^M

Running test 1 for exception 0x00: l1_dataA^M

... PASS (test completed 1/1 times, as expected by signal 0: Unknown signal

0)^M

^M

...Running test 87 for exception 0x3f: Stack push to non-existant L1^M

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)^M

^M

88/88 tests passed^M

root:/bin>

Case 2 ...PASS

 

 

taskset 2 ./traps_test -1^M

^M

Running test 0 for exception 0x00: flush scratch pad^M

... PASS (test completed 1/1 times, as expected by signal 0: Unknown signal

0)^M

^M

Running test 1 for exception 0x00: l1_dataA^M

... PASS (test completed 1/1 times, as expected by signal 0: Unknown signal

0)^M

^M

Running test 2 for exception 0x00: l1_dataB^M

... PASS (test completed 1/1 times, as expected by signal 0: Unknown signal

0)^M

^M

Running test 3 for exception 0x00: l1_instruction^M

... PASS (test completed 1/1 times, as expected by signal 0: Unknown signal

0)^M

..Running test 87 for exception 0x3f: Stack push to non-existant L1^M

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)^M

^M

88/88 tests passed^M

root:/bin>

 

It does not support running migrate.

 

So close now.

 

 

 

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