[#5515] 4 more trap cases fails on bf533

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[#5515] 4 more trap cases fails on bf533

Submitted By: Mingquan Pan

Open Date

2009-09-04 01:52:47     Close Date

2010-07-23 15:23:40

Priority:

Medium     Assignee:

Robin Getz

Status:

Closed     Fixed In Release:

N/A

Found In Release:

2010R1     Release:

Category:

N/A     Board:

N/A

Processor:

BF533     Silicon Revision:

Is this bug repeatable?:

Yes     Resolution:

Duplicate

Uboot version or rev.:

    Toolchain version or rev.:

09r1-rc9

App binary format:

N/A     

Summary: 4 more trap cases fails on bf533

Details:

 

4 more trap cases fails on revision 0.3 bf533 ezkit and bf533 stamp.

 

Boot Mode: 0^M

Reset caused by Software reset^M

Blackfin support (C) 2004-2009 Analog Devices, Inc.^M

Compiled for ADSP-BF533 Rev 0.3^M

Blackfin Linux support by http://blackfin.uclinux.org/^M

Processor Speed: 497 MHz core clock and 99 MHz System Clock^M

NOMPU: setting up cplb tables^M

Instruction Cache Enabled for CPU0^M

  External memory: cacheable in instruction cache^M

Data Cache Enabled for CPU0^M

...

 

Running test 50 for exception 0x24: Data read misaligned address violation^M

... FAIL (test failed with wrong EXCAUSE, expected 24, but got 3f)^M

FAIL (test failed with wrong EXCAUSE, expected 0x24, but got 0x3f)^M

FAIL (test completed properly 0/1 times)^M

^M

Running test 51 for exception 0x24: Data write misaligned address violation^M

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)^M

^M

Running test 52 for exception 0x24: Stack set to odd address - misaligned address violation^M

... FAIL (test failed with wrong EXCAUSE, expected 24, but got 3f)^M

FAIL (test failed with wrong EXCAUSE, expected 0x24, but got 0x3f)^M

FAIL (test completed properly 0/1 times)^M

^M

Running test 53 for exception 0x24: Stack push to odd address^M

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)^M

^M

Running test 54 for exception 0x26: Data Read CPLB miss^M

... FAIL (test failed with wrong EXCAUSE, expected 26, but got 3f)^M

FAIL (test failed with wrong EXCAUSE, expected 0x26, but got 0x3f)^M

FAIL (test completed properly 0/1 times)^M

^M

Running test 55 for exception 0x26: Data Write CPLB miss^M

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)^M

^M

Running test 56 for exception 0x26: Stack CPLB miss^M

... FAIL (test failed with wrong EXCAUSE, expected 26, but got 3f)^M

FAIL (test failed with wrong EXCAUSE, expected 0x26, but got 0x3f)^M

FAIL (test completed properly 0/1 times)^M

^M

 

Follow-ups

 

--- Robin Getz                                               2009-09-08 18:43:43

Hmm....

 

Are things any different on 0.3 vs 0.5?

 

--- Mingquan Pan                                             2009-09-09 00:54:59

It looks the same bf533 ezkit kernel running on 0.5 silicon, these cases are not

failed.

 

lackfin support (C) 2004-2009 Analog Devices, Inc.

Compiled for ADSP-BF533 Rev 0.3

Warning: Compiled for Rev 3, but running on Rev 5

Blackfin Linux support by http://blackfin.uclinux.org/                        

                                                                          

...

Running test 50 for exception 0x24: Data read misaligned address violation

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

 

Running test 51 for exception 0x24: Data write misaligned address violation

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

 

Running test 52 for exception 0x24: Stack set to odd address - misaligned

address violation

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

 

Running test 53 for exception 0x24: Stack push to odd address

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

 

Running test 54 for exception 0x26: Data Read CPLB miss

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

 

Running test 55 for exception 0x26: Data Write CPLB miss

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

 

Running test 56 for exception 0x26: Stack CPLB miss

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

 

Running test 57 for exception 0x26: Stack push to miss

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)       

                                                                          

 

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

 

94/95 tests passed

 

So we change to use 0.5 instead of 0.3 chip?

 

--- Robin Getz                                               2009-09-10 12:13:30

No -- I need to figure out what anomaly is causing the problem first ----

Although I'm not sure what we can do about things at the moment...

 

-Robin

 

--- Robin Getz                                               2010-07-23 15:23:40

This is a dup of something Barry is working on.

 

-Robin

 

 

 

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