[#5412] Kernel image for g729 test can not boot up in branch

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[#5412] Kernel image for g729 test can not boot up in branch

Submitted By: Vivi Li

Open Date

2009-08-03 00:39:14     Close Date

2009-08-11 17:14:48

Priority:

Medium High     Assignee:

Yi Li

Status:

Closed     Fixed In Release:

N/A

Found In Release:

N/A     Release:

Category:

N/A     Board:

N/A

Processor:

ALL     Silicon Revision:

Is this bug repeatable?:

Yes     Resolution:

Fixed

Uboot version or rev.:

    Toolchain version or rev.:

gcc4.1_2009r1-rc9

App binary format:

N/A     

Summary: Kernel image for g729 test can not boot up in branch

Details:

 

Kernel image for g729 test can not boot up in branch.

 

Bellow is the log:

--

Linux version 2.6.28.10-ADI-2009R1-svn7092 (test@uclinux54-adv7393-ad1981-usb1362) (gcc version 4.1.2 (ADI svn)) #68 Sun Aug 2 19

bootconsole [early_shadow0] enabled

bootconsole [early_BFuart0] enabled

early printk enabled on early_BFuart0

Warning: limiting memory to 56MB due to hardware anomaly 05000263

Board Memory: 64MB

Kernel Managed Memory: 64MB

Memory map:

  fixedcode = 0x00000400-0x00000490

  text      = 0x00001000-0x00106e50

  rodata    = 0x00106e50-0x00157c40

  bss       = 0x00158000-0x00169720

  data      = 0x00169720-0x0017a000

    stack   = 0x00178000-0x0017a000

  init      = 0x0017a000-0x008c1000

  available = 0x008c1000-0x037ff000

  DMA Zone  = 0x03f00000-0x04000000

Hardware Trace Active and Enabled

Boot Mode: 0

Blackfin support (C) 2004-2009 Analog Devices, Inc.

Compiled for ADSP-BF537 Rev 0.2

Blackfin Linux support by http://blackfin.uclinux.org/

Processor Speed: 500 MHz core clock and 125 MHz System Clock

NOMPU: setting up cplb tables

Instruction Cache Enabled for CPU0

Data Cache Enabled for CPU0 (write-back)

Built 1 zonelists in Zone order, mobility grouping off.  Total pages: 14223

Kernel command line: root=/dev/mtdblock0 rw clkin_hz=25000000 earlyprintk=serial,uart0,57600 console=ttyBF0,57600 ip=10.100.4.50f

Configuring Blackfin Priority Driven Interrupts

PID hash table entries: 256 (order: 8, 1024 bytes)

console handover:boot [early_BFuart0] boot [early_shadow0]  -> real [ttyBF0]

Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)

Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)

Memory available: 47808k/65536k RAM, (7452k init code, 1047k kernel code, 461k data, 1024k dma, 7744k reserved)

Calibrating delay loop... 995.32 BogoMIPS (lpj=1990656)

Security Framework initialized

Mount-cache hash table entries: 512

Blackfin Scratchpad data SRAM: 4 KB

Blackfin L1 Data A SRAM: 16 KB (16 KB free)

Blackfin L1 Data B SRAM: 16 KB (16 KB free)

Blackfin L1 Instruction SRAM: 48 KB (47 KB free)

net_namespace: 288 bytes

NET: Registered protocol family 16

Blackfin DMA Controller

stamp_init(): registering device resources

NET: Registered protocol family 2

IP route cache hash table entries: 1024 (order: 0, 4096 bytes)

TCP established hash table entries: 2048 (order: 2, 16384 bytes)

TCP bind hash table entries: 2048 (order: 1, 8192 bytes)

TCP: Hash tables configured (established 2048 bind 2048)

TCP reno registered

NET: Registered protocol family 1

msgmni has been set to 93

io scheduler noop registered

io scheduler anticipatory registered (default)

io scheduler cfq registered

Serial: Blackfin serial driver

bfin-uart.1: ttyBF0 at MMIO 0xffc00400 (irq = 18) is a BFIN-UART

brd: module loaded

bfin_mii_bus: probed

bfin_mac: attached PHY driver [SMSC LAN83C185] (mii_bus:phy_addr=0:01, irq=-1, mdc_clk=2500000Hz(mdc_div=24)@sclk=125MHz)

bfin_mac bfin_mac.0: Blackfin on-chip Ethernet MAC driver, Version 1.1

bfin-spi bfin-spi.0: Blackfin on-chip SPI Controller Driver, Version 1.0, regs_base@ffc00500, dma channel@7

rtc-bfin rtc-bfin: rtc core: registered rtc-bfin as rtc0

bfin-wdt: initialized: timeout=20 sec (nowayout=0)

TCP cubic registered

NET: Registered protocol family 17

--

 

Follow-ups

 

--- Yi Li                                                    2009-08-04 04:08:31

I can reproduce this bug on BF537-STAMP (chip rev. 0.2). This does not related

much with g729, but with L1 memory.

 

If we do not put kernel functions in L1, i.e., if configure kernel as:

 

# CONFIG_I_ENTRY_L1 is not set

# CONFIG_EXCPT_IRQ_SYSC_L1 is not set

# CONFIG_DO_IRQ_L1 is not set

# CONFIG_CORE_TIMER_IRQ_L1 is not set

# CONFIG_IDLE_L1 is not set

# CONFIG_SCHEDULE_L1 is not set

# CONFIG_ARITHMETIC_OPS_L1 is not set

# CONFIG_ACCESS_OK_L1 is not set

# CONFIG_MEMSET_L1 is not set

# CONFIG_MEMCPY_L1 is not set

# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set

# CONFIG_IP_CHECKSUM_L1 is not set

 

Kernel will hang at:

 

cplb-nompu/cplbmgr.c: write_icplb_data()

 

bfin_write32(ICPLB_ADDR0 + idx * 4, addr);

 

 

GDB:

 

(gdb) c

Continuing.

^C

Program received signal SIGINT, Interrupt.

cplb_hdr (seqstat=<value optimized out>, regs=<value optimized

out>)

    at arch/blackfin/kernel/cplb-nompu/cplbmgr.c:96

96        bfin_write_IMEM_CONTROL_SSYNC(ctrl);

1: x/i $pc  0xaa60 <cplb_hdr+472>:    SSYNC;

(gdb)

 

 

disassemble:

 

    aa2e:       48 e1 e0 ff     P0.H = 0xffe0;          /* (-32)      

P0=0xffe00004(-2097148) */

    aa32:       11 93           [P2] = R1;

    aa34:       08 e1 04 10     P0.L = 0x1004;          /* (4100)     

P0=0xffe01004(-2093052) */

    aa38:       01 91           R1 = [P0];

    aa3a:       24 00           SSYNC;

    aa3c:       01 30           R0 = R1;

    aa3e:       08 4c           BITCLR (R0, 0x1);               /* bit  1 */

    aa40:       00 93           [P0] = R0;

    aa42:       24 00           SSYNC;

    aa44:       12 32           P2 = R2;

    aa46:       51 44           P1 = P2 << 0x2;

    aa48:       4a e1 e0 ff     P2.H = 0xffe0;          /* (-32)      

P2=0xffe0e300(-2039040) */

    aa4c:       0a e1 00 12     P2.L = 0x1200;          /* (4608)     

P2=0xffe01200(-2092544) */

    aa50:       91 5a           P2 = P1 + P2;

    aa52:       16 93           [P2] = R6;

    aa54:       4a e1 e0 ff     P2.H = 0xffe0;          /* (-32)      

P2=0xffe01200(-2092544) */

    aa58:       0a e1 00 11     P2.L = 0x1100;          /* (4352)     

P2=0xffe01100(-2092800) */

    aa5c:       51 5a           P1 = P1 + P2;

    aa5e:       0b 93           [P1] = R3;

    aa60:       24 00           SSYNC;        <============= Hang here

 

 

However, if I using gdb/gnice "si" (step instruction), the kernel

will finally boot up. This looks like an anomaly.

 

 

 

--- Yi Li                                                    2009-08-07 03:18:55

As pointed out by Robin, this bug may be caused by anomaly 05000402:

 

- SSYNC Stalls Processor when Executed from Non-Cacheable non-L1 Memory.

 

Gdb shows the kernel hangs at the \"SSYNC\" before (not after)

writing

IMEM_CONTROL to enable CPLB.

 

\"

    aa2e:       48 e1 e0 ff     P0.H = 0xffe0;          /* (-32)

P0=0xffe00004(-2097148) */

    aa32:       11 93           [P2] = R1;

    aa34:       08 e1 04 10     P0.L = 0x1004;          /* (4100)

P0=0xffe01004(-2093052) */

    aa38:       01 91           R1 = [P0];

    aa3a:       24 00           SSYNC;               

    aa3c:       01 30           R0 = R1;

    aa3e:       08 4c           BITCLR (R0, 0x1);               /* bit

1 */

    aa40:       00 93           [P0] = R0;

    aa42:       24 00           SSYNC;

    aa44:       12 32           P2 = R2;

    aa46:       51 44           P1 = P2 << 0x2;

    aa48:       4a e1 e0 ff     P2.H = 0xffe0;          /* (-32)

P2=0xffe0e300(-2039040) */

    aa4c:       0a e1 00 12     P2.L = 0x1200;          /* (4608)

P2=0xffe01200(-2092544) */

    aa50:       91 5a           P2 = P1 + P2;

    aa52:       16 93           [P2] = R6;

    aa54:       4a e1 e0 ff     P2.H = 0xffe0;          /* (-32)

P2=0xffe01200(-2092544) */

    aa58:       0a e1 00 11     P2.L = 0x1100;          /* (4352)

P2=0xffe01100(-2092800) */

    aa5c:       51 5a           P1 = P1 + P2;

    aa5e:       0b 93           [P1] = R3;

    aa60:       24 00           SSYNC;    /* <=============== kernel

hangs at this SSYNC before writing to IMEM_CONTROL */

    aa62:       01 93           [P0] = R1;

    aa64:       24 00           SSYNC;

 

According to PRM(6-7):

\"CPLBs must be disabled using this bit prior to updating their

descriptors (DCPLB_DATAx and DCPLB_ADDRx registers). Note since load

store ordering is weak (see “Ordering of Loads and Stores” on page

6-69), disabling of CPLBs should be proceeded by a CSYNC.\"

 

After change the \"SSYNC\"(\"__asm__ volatime

(\"ssync\")\") before writing IMEM_CONTROL to \"CSYNC\"

(CSYNC() with workaround for anomaly), this bug disappear.

 

--- Yi Li                                                    2009-08-07 03:21:58

One of the workaround for this bug is in mach-common/arch_check.c, force

enabling \"CONFIG_EXCPT_IRQ_SYSC_L1\"

 

/* If CPLB miss exception handler is not in L1, anomaly 05000402 will be hit -

Execution of SSYNC before CPLB is enabled */

#if ANOMALY_05000402 && !defined(CONFIG_EXCPT_IRQ_SYSC_L1)

#error You are using a part with anomaly 05000402. Please enable

CONFIG_EXCPT_IRQ_SYSC_L1.

#endif

 

But since we have replaced \"SSYNC\" before writing IMEM_CONTROL with

CSYNC, this workaround can be dropped.

 

--- Vivi Li                                                  2009-08-11 22:15:03

OK now. Close it.

 

 

 

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File Name     File Type     File Size     Posted By

config.g729    application/octet-stream    32893    Vivi Li

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