[#5326] cpufreq-set can change cpu freq but bogomips remains

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[#5326] cpufreq-set can change cpu freq but bogomips remains

Submitted By: Mingquan Pan

Open Date

2009-07-08 03:26:56     Close Date

2009-08-09 23:20:05

Priority:

Medium High     Assignee:

Mike Frysinger

Graf Yang

Michael Hennerich

Status:

Closed     Fixed In Release:

N/A

Found In Release:

N/A     Release:

Category:

N/A     Board:

N/A

Processor:

BF537     Silicon Revision:

Is this bug repeatable?:

Yes     Resolution:

Rejected

Uboot version or rev.:

    Toolchain version or rev.:

09R1-RC9

App binary format:

N/A     

Summary: cpufreq-set can change cpu freq but bogomips remains

Details:

 

cpufreq-set can change cpu freq but bogomips remains. Should it change as well?

 

cat /proc/cpuinfo

processor       : 0

vendor_id       : Analog Devices

cpu family      : 0x27c8

model name      : ADSP-BF537 500(MHz CCLK) 125(MHz SCLK) (mpu off)

stepping        : 2

cpu MHz         : 500.000/125.000

Case 3 ...PASS

 

Case 3 ...PASS

 

cat cpuinfo case pass!

 

bogomips        : 997.37

Calibration     : 498688000 loops

cache size      : 16 KB(L1 icache) 32 KB(L1 dcache-wb) 0 KB(L2 cache)

dbank-A/B       : cache/cache

icache setup    : 4 Sub-banks/4 Ways, 32 Lines/Way

dcache setup    : 2 Super-banks/4 Sub-banks/2 Ways, 64 Lines/Way

board name      : ADI BF537-STAMP

board memory    : 65536 kB (0x00000000 -> 0x04000000)

kernel memory   : 57336 kB (0x00001000 -> 0x037ff000)

 

root:/usr/bin> cpufreq-set -f 250000

root:/usr/bin>

Case 4 ...PASS

 

Case 4 ...PASS

cat /proc/cpuinfo

processor       : 0

vendor_id       : Analog Devices

cpu family      : 0x27c8

model name      : ADSP-BF537 250(MHz CCLK) 125(MHz SCLK) (mpu off)

stepping        : 2

cpu MHz         : 250.000/125.000

bogomips        : 997.37

Calibration     : 498688000 loops

cache size      : 16 KB(L1 icache) 32 KB(L1 dcache-wb) 0 KB(L2 cache)

dbank-A/B       : cache/cache

icache setup    : 4 Sub-banks/4 Ways, 32 Lines/Way

dcache setup    : 2 Super-banks/4 Sub-banks/2 Ways, 64 Lines/Way

board name      : ADI BF537-STAMP

board memory    : 65536 kB (0x00000000 -> 0x04000000)

kernel memory   : 57336 kB (0x00001000 -> 0x037ff000)

 

root:/usr/bin>

Case 5 ...PASS

 

Case 5 ...PASS

cd /sys/devices/system/cpu/cpu0/cpufreq/

root:/sys/devices/system/cpu/cpu0/cpufreq> cat scaling_governor

userspace

root:/sys/devices/system/cpu/cpu0/cpufreq>

Case 6 ...PASS

 

Case 6 ...PASS

cat stats/*

500000 1031

250000 527

1

root:/sys/devices/system/cpu/cpu0/cpufreq>

 

 

Follow-ups

 

--- Michael Hennerich                                        2009-07-08 04:27:25

During CPU frequency transitions the kernel adjusts only loops_per_jiffy.

But in show_cpuinfo we print out cpudata->loops_per_jiffy, which is only

initialized once, during boot.

 

IMHO it doesn’t make sense on Blackfin to use on a per_cpu basis

loops_per_jiffy, since both cores always run on the same CCLK domain. In

addition the current implementation has flaws since the main consumer for

loops_per_jiffy (asm/delay.h) uses the global kernel loops_per_jiffy and not the

per_cpu one.

 

I would vote that we change show_cpuinfo to use loops_per_jiffy.

 

Comments appreciated.

 

Adding Mike and Graf

 

-Michael

 

--- Mike Frysinger                                           2009-07-08 14:38:49

if we dont allow per-cpu cclk scaling, then it doesnt make sense to have per-cpu

loops_per_jiffy

 

--- Graf Yang                                                2009-07-08 22:30:24

No objection.

 

--- Michael Hennerich                                        2009-07-09 05:59:23

Fixed on trunk and branch 2009R1

 

--- Mingquan Pan                                             2009-07-13 00:06:18

Yes, it fixed on branch head. like on bf537 board:

 

root:/usr/bin> cpufreq-info

cpufrequtils 005: cpufreq-info (C) Dominik Brodowski 2004-2006

Report errors and bugs to cpufreq@vger.kernel.org, please.

analyzing CPU 0:

  driver: bfin cpufreq

  CPUs which need to switch frequency at the same time: 0

  hardware limits: 250 MHz - 500 MHz

  available frequency steps: 500 MHz, 250 MHz

  available cpufreq governors: userspace

  current policy: frequency should be within 250 MHz and 500 MHz.

                  The governor "userspace" may decide which speed to

use

                  within this range.

  current CPU frequency is 500 MHz (asserted by call to hardware).

  cpufreq stats: 500 MHz:100.00%, 250 MHz:0.00%

root:/usr/bin>

Case 2 ...PASS

 

Case 2 ...PASS

cat /proc/cpuinfo

processor       : 0

vendor_id       : Analog Devices

cpu family      : 0x27c8

model name      : ADSP-BF537 500(MHz CCLK) 125(MHz SCLK) (mpu off)

stepping        : 2

cpu MHz         : 500.000/

Case 3 ...PASS

 

Case 3 ...PASS

 

cat cpuinfo case pass!

125.000

bogomips        : 995.32

Calibration     : 497664000 loops

cache size      : 16 KB(L1 icache) 32 KB(L1 dcache-wb) 0 KB(L2 cache)

dbank-A/B       : cache/cache

icache setup    : 4 Sub-banks/4 Ways, 32 Lines/Way

dcache setup    : 2 Super-banks/4 Sub-banks/2 Ways, 64 Lines/Way

board name      : ADI BF537-STAMP

board memory    : 65536 kB (0x00000000 -> 0x04000000)

kernel memory   : 57336 kB (0x00001000 -> 0x037ff000)

 

root:/usr/bin> cpufreq-set -f 250000

root:/usr/bin>

Case 4 ...PASS

 

Case 4 ...PASS

cat /proc/cpuinfo

processor       : 0

vendor_id       : Analog Devices

cpu family      : 0x27c8

model name      : ADSP-BF537 250(MHz CCLK) 125(MHz SCLK) (mpu off)

stepping        : 2

cpu MHz         : 250.000/125.000

bogomips        : 497.66

Calibration     : 248832000 loops

cache size      : 16 KB(L1 icache) 32 KB(L1 dcache-wb) 0 KB(L2 cache)

dbank-A/B       : cache/cache

icache setup    : 4 Sub-banks/4 Ways, 32 Lines/Way

dcache setup    : 2 Super-banks/4 Sub-banks/2 Ways, 64 Lines/Way

board name      : ADI BF537-STAMP

board memory    : 65536 kB (0x00000000 -> 0x04000000)

kernel memory   : 57336 kB (0x00001000 -> 0x037ff000)

 

root:/usr/bin>

Case 5 ...PASS

 

Case 5 ...PASS

cd /sys/devices/system/cpu/cpu0/cpufreq/

root:/sys/devices/system/cpu/cpu0/cpufreq> cat scaling_governor

userspace

root:/sys/devices/system/cpu/cpu0/cpufreq>

Case 6 ...PASS

 

Case 6 ...PASS

cat stats/*

500000 1032

250000 529

1

 

So close.

 

--- Mingquan Pan                                             2009-08-06 05:02:36

It looks the fix doesn\'t works for bf561 SMP kernel, the cpu mhz changes but

the bogomips for both of the cores remains.

 

dmesg

Linux version 2.6.28.10-ADI-2009R1-svn7103 (test@uclinux65-561-SMP) (gcc

version 4.1.2 (ADI svn)) #71 SMP Tue Aug 4 11:55:02 GMT 2009

bootconsole [early_shadow0] enabled

bootconsole [early_BFuart0] enabled

early printk enabled on early_BFuart0

Board Memory: 64MB

Kernel Managed Memory: 64MB

Memory map:

  fixedcode = 0x00000400-0x00000490

  text      = 0x00001000-0x00105d80

  rodata    = 0x00105d80-0x001545ec

  bss       = 0x00155000-0x00167184

  data      = 0x001671a0-0x0017a000

    stack   = 0x00178000-0x0017a000

  init      = 0x0017a000-0x00764000

  available = 0x00764000-0x03eff000

  DMA Zone  = 0x03f00000-0x04000000

Hardware Trace Active and Enabled

Boot Mode: 0

Reset caused by Software reset

Blackfin support (C) 2004-2009 Analog Devices, Inc.

Compiled for ADSP-BF561 Rev 0.5

Blackfin Linux support by http://blackfin.uclinux.org/

Processor Speed: 600 MHz core clock and 100 MHz System Clock

boot memmap: 0000000000764000 - 0000000003eff000 (usable)

On node 0 totalpages: 16127

free_area_init_node: node 0, pgdat 00175680, node_mem_map 00766000

  DMA zone: 126 pages used for memmap

  DMA zone: 0 pages reserved

  DMA zone: 16001 pages, LIFO batch:3

  Normal zone: 0 pages used for memmap

  Movable zone: 0 pages used for memmap

NOMPU: setting up cplb tables

NOMPU: setting up cplb tables

Instruction Cache Enabled for CPU0

Data Cache Enabled for CPU0 (write-through)

Built 1 zonelists in Zone order, mobility grouping off.  Total pages: 16001

Kernel command line: root=/dev/mtdblock0 rw earlyprintk=serial,uart0,57600

ip=10.100.4.50:10.100.4.174:10.100.4.174:255.255.255.0:bf561-ezkit:eth0:off

Configuring Blackfin Priority Driven Interrupts

PID hash table entries: 256 (order: 8, 1024 bytes)

console handover:boot [early_BFuart0] boot [early_shadow0]  -> real

[ttyBF0]

Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)

Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)

Kernel managed physical pages: 16127

Memory available: 56344k/65536k RAM, (6056k init code, 1043k kernel code, 465k

data, 1024k dma, 600k reserved)

Calibrating delay loop... 1191.93 BogoMIPS (lpj=2383872)

Security Framework initialized

Mount-cache hash table entries: 512

CoreB bootstrap code to SRAM ff600000 via DMA.

Booting Core B.

Instruction Cache Enabled for CPU1

Data Cache Enabled for CPU1 (write-through)

Calibrating delay loop... 1191.93 BogoMIPS (lpj=2383872)

Brought up 2 CPUs

SMP: Total of 2 processors activated (2383.87 BogoMIPS).

CPU0 attaching sched-domain:

domain 0: span 0-1 level CPU

  groups: 0 1

CPU1 attaching sched-domain:

domain 0: span 0-1 level CPU

  groups: 1 0

Blackfin Scratchpad data SRAM: 4 KB

Blackfin Scratchpad data SRAM: 4 KB

Blackfin L1 Data A SRAM: 16 KB (16 KB free)

Blackfin L1 Data A SRAM: 16 KB (16 KB free)

Blackfin L1 Data B SRAM: 16 KB (16 KB free)

Blackfin L1 Data B SRAM: 16 KB (16 KB free)

Blackfin L1 Instruction SRAM: 16 KB (15 KB free)

Blackfin L1 Instruction SRAM: 16 KB (15 KB free)

Blackfin L2 SRAM: 128 KB (127 KB free)

net_namespace: 296 bytes

NET: Registered protocol family 16

Blackfin DMA Controller

ezkit_init(): registering device resources

NET: Registered protocol family 2

IP route cache hash table entries: 1024 (order: 0, 4096 bytes)

TCP established hash table entries: 2048 (order: 2, 16384 bytes)

TCP bind hash table entries: 2048 (order: 2, 16384 bytes)

TCP: Hash tables configured (established 2048 bind 2048)

TCP reno registered

NET: Registered protocol family 1

Setting up Blackfin MMR debugfs

msgmni has been set to 110

io scheduler noop registered

io scheduler anticipatory registered (default)

io scheduler cfq registered

Serial: Blackfin serial driver

bfin-uart.1: ttyBF0 at MMIO 0xffc00400 (irq = 35) is a BFIN-UART

brd: module loaded

smc91x.c: v1.1, sep 22 2004 by Nicolas Pitre <nico@cam.org>

eth0: SMC91C11xFD (rev 2) at 2c010300 IRQ 82 [nowait]

eth0: Ethernet addr: 00:e0:22:fe:ba:2a

eth0: PHY LAN83C183 (LAN91C111 Internal)

bfin-spi bfin-spi.0: Blackfin on-chip SPI Controller Driver, Version 1.0,

regs_base@ffc00500, dma channel@16

bfin-wdt: initialized: timeout=20 sec (nowayout=0)

TCP cubic registered

NET: Registered protocol family 17

eth0: link down

IP-Config: Complete:

     device=eth0, addr=10.100.4.50, mask=255.255.255.0, gw=10.100.4.174,

     host=bf561-ezkit, domain=, nis-domain=(none),

     bootserver=10.100.4.174, rootserver=10.100.4.174, rootpath=

Freeing unused kernel memory: 6056k freed

dma_alloc_init: dma_page @ 0x00761000 - 256 pages at 0x03f00000

eth0: link up, 100Mbps, full-duplex, lpa 0x41E1

root:/>

Case 1 ...PASS

 

Case 1 ...PASS

cd /usr/bin

root:/usr/bin> cpufreq-info

cpufrequtils 005: cpufreq-info (C) Dominik Brodowski 2004-2006

Report errors and bugs to cpufreq@vger.kernel.org, please.

analyzing CPU 0:

  driver: bfin cpufreq

  CPUs which need to switch frequency at the same time: 0

  hardware limits: 300 MHz - 600 MHz

  available frequency steps: 600 MHz, 300 MHz

  available cpufreq governors: userspace

  current policy: frequency should be within 300 MHz and 600 MHz.

                  The governor \"userspace\" may decide which speed

to use

                  within this range.

  current CPU frequency is 600 MHz (asserted by call to hardware).

  cpufreq stats: 600 MHz:100.00%, 300 MHz:0.00%

analyzing CPU 1:

  no or unknown cpufreq driver is active on this CPU

root:/usr/bin>

Case 2 ...PASS

 

Case 2 ...PASS

cat /proc/cpuinfo

processor       : 0

vendor_id       : Analog Devices

cpu family      : 0x27bb

model name      : ADSP-BF561 600(MHz CCLK) 100(MHz SCLK) (mpu off)

stepping        : 5

cpu MHz         : 600.000/100.000

bogomips        : 1191.93

Calibration     : 595968000 loops

cache size      : 16 KB(L

Case 3 ...PASS

 

Case 3 ...PASS

 

exact_core_clock 600.000

 

calibration_before 595968000

 

cat cpuinfo case pass!

1 icache) 32 KB(L1 dcache-wt) 0 KB(L2 cache)

dbank-A/B       : cache/cache

icache setup    : 4 Sub-banks/4 Ways, 32 Lines/Way

dcache setup    : 2 Super-banks/4 Sub-banks/2 Ways, 64 Lines/Way

SMP Dcache Flushes      : 8238

 

SMP Icache Flushes      : 0

 

processor       : 1

vendor_id       : Analog Devices

cpu family      : 0x27bb

model name      : ADSP-BF561 600(MHz CCLK) 100(MHz SCLK) (mpu off)

stepping        : 5

cpu MHz         : 600.000/100.000

bogomips        : 1191.93

Calibration     : 595968000 loops

cache size      : 16 KB(L1 icache) 32 KB(L1 dcache-wt) 0 KB(L2 cache)

dbank-A/B       : cache/cache

icache setup    : 4 Sub-banks/4 Ways, 32 Lines/Way

dcache setup    : 2 Super-banks/4 Sub-banks/2 Ways, 64 Lines/Way

SMP Dcache Flushes      : 8389

 

SMP Icache Flushes      : 0

 

L2 SRAM         : 128KB

board name      : ADI BF561-EZKIT

board memory    : 65536 kB (0x00000000 -> 0x04000000)

kernel memory   : 64504 kB (0x00001000 -> 0x03eff000)

 

root:/usr/bin> cpufreq-set -f 300000

root:/usr/bin>

Case 4 ...PASS

 

Case 4 ...PASS

cat /proc/cpuinfo

processor       : 0

vendor_id       : Analog Devices

cpu family      : 0x27bb

model name      : ADSP-BF561 300(MHz CCLK) 100(MHz SCLK) (mpu off)

stepping        : 5

cpu MHz         : 300.000/100.000

bogomips        : 1191.93

Calibration     : 595968000 loops

cache size      : 16 KB(L1 icache) 32 KB(L1 dcache-wt) 0 KB(L2 cache)

dbank-A/B       : cache/cache

icache setup    : 4 Sub-banks/4 Ways, 32 Lines/Way

dcache setup    : 2 Super-banks/4 Sub-banks/2 Ways, 64 Lines/Way

SMP Dcache Flushes      : 10564

 

SMP Icache Flushes      : 0

 

processor       : 1

vendor_id       : Analog Devices

cpu family      : 0x27bb

model name      : ADSP-BF561 300(MHz CCLK) 100(MHz SCLK) (mpu off)

stepping        : 5

cpu MHz         : 300.000/100.000

bogomips        : 1191.93

Calibration     : 595968000 loops

cache size      : 16 KB(L1 icache) 32 KB(L1 dcache-wt) 0 KB(L2 cache)

dbank-A/B       : cache/cache

icache setup    : 4 Sub-banks/4 Ways, 32 Lines/Way

dcache setup    : 2 Super-banks/4 Sub-banks/2 Ways, 64 Lines/Way

SMP Dcache Flushes      : 10740

 

SMP Icache Flushes      : 0

 

L2 SRAM         : 128KB

board name      : ADI BF561-EZKIT

board memory    : 65536 kB (0x00000000 -> 0x04000000)

kernel memory   : 64504 kB (0x00001000 -> 0x03eff000)

 

 

--- Graf Yang                                                2009-08-07 04:33:38

Our cpufreq driver currently only support one cpu.

Mainline code currently not change loops_per_jiffy in SMP kernel.

 

So run cpufreq-set on SMP is meanless for now.

 

--- Mingquan Pan                                             2009-08-10 04:20:15

ok, so skip this case for now.

 

 

 

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File Name     File Type     File Size     Posted By

config.change_cpufreq    application/octet-stream    33333    Mingquan Pan

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