[#5314] dmacopy failed on bf548-ezkit when copy between L2 and SDRAM

Document created by Aaronwu Employee on Sep 4, 2013
Version 1Show Document
  • View in full screen mode

[#5314] dmacopy failed on bf548-ezkit when copy between L2 and SDRAM

Submitted By: Vivi Li

Open Date

2009-07-06 05:22:42     Close Date

2010-07-22 03:48:59

Priority:

Low     Assignee:

Nobody

Status:

Closed     Fixed In Release:

N/A

Found In Release:

2009R1-RC6     Release:

Category:

Tests     Board:

EZKIT Lite

Processor:

BF548     Silicon Revision:

Is this bug repeatable?:

Yes     Resolution:

Out of Date

Uboot version or rev.:

    Toolchain version or rev.:

gcc4.1_09r1-rc7

App binary format:

N/A     

Summary: dmacopy failed on bf548-ezkit when copy between L2 and SDRAM

Details:

 

dmacopy test failed for bf548-ezkit when copy between L2 and SDRAM.

As the last passed result is on about 2009_May_06, is this bug related to bug [#5133]?

 

Config file is attached and bellow is the log:

--

Linux version 2.6.28.10-ADI-2009R1-svn6917 (test@uclinux61-bf548-std) (gcc version 4.1.2 (ADI svn)) #16 Sat Jul 4 07:45:00 GMT 2009^M

console [early_BFuart0] enabled^M

early printk enabled on early_BFuart0^M

Board Memory: 64MB^M

Kernel Managed Memory: 64MB^M

Memory map:^M

  fixedcode = 0x00000400-0x00000490^M

  text      = 0x00001000-0x001973c0^M

  rodata    = 0x001973c0-0x002229f8^M

  bss       = 0x00223000-0x00237150^M

  data      = 0x00237150-0x00252000^M

    stack   = 0x00250000-0x00252000^M

  init      = 0x00252000-0x009fb000^M

  available = 0x009fb000-0x03dff000^M

  DMA Zone  = 0x03e00000-0x04000000^M

Hardware Trace Active and Enabled^M

Boot Mode: 1^M

Recovering from Watchdog event^M

Blackfin support (C) 2004-2009 Analog Devices, Inc.^M

Compiled for ADSP-BF548 Rev 0.2^M

Blackfin Linux support by http://blackfin.uclinux.org/^M

Processor Speed: 525 MHz core clock and 131 MHz System Clock^M

NOMPU: setting up cplb tables^M

Instruction Cache Enabled for CPU0^M

Data Cache Enabled for CPU0 (write-back)^M

Data Cache (L2 SRAM) Enabled (write-back)^M

Built 1 zonelists in Zone order, mobility grouping off.  Total pages: 15747^M

Kernel command line: root=/dev/mtdblock0 rw earlyprintk=serial,uart0,57600 ip=10.100.4.50:10.100.4.174:10.100.4.174:255.255.255.0:bf548-ezkit:eth0:off^M

Configuring Blackfin Priority Driven Interrupts^M

PID hash table entries: 256 (order: 8, 1024 bytes)^M

console handover: boot [early_BFuart0] -> real [ttyBF0]^M

Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)^M

Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)^M

Memory available: 52696k/65536k RAM, (7844k init code, 1624k kernel code, 748k data, 2048k dma, 572k reserved)^M

Calibrating delay loop... 1046.52 BogoMIPS (lpj=2093056)^M

Security Framework initialized^M

Mount-cache hash table entries: 512^M

Blackfin Scratchpad data SRAM: 4 KB^M

Blackfin L1 Data A SRAM: 16 KB (15 KB free)^M

Blackfin L1 Data B SRAM: 16 KB (16 KB free)^M

Blackfin L1 Instruction SRAM: 48 KB (42 KB free)^M

Blackfin L2 SRAM: 128 KB (128 KB free)^M

net_namespace: 288 bytes^M

NET: Registered protocol family 16^M

Blackfin DMA Controller^M

ezkit_init(): registering device resources^M

SCSI subsystem initialized^M

usbcore: registered new interface driver usbfs^M

usbcore: registered new interface driver hub^M

usbcore: registered new device driver usb^M

musb_hdrc: version 6.0, musb-dma, host, debug=0^M

musb_hdrc: USB Host mode controller at ffc03c00 using DMA, IRQ 82^M

musb_hdrc musb_hdrc.0: MUSB HDRC host driver^M

musb_hdrc musb_hdrc.0: new USB bus registered, assigned bus number 1^M

usb usb1: configuration #1 chosen from 1 choice^M

hub 1-0:1.0: USB hub found^M

dma_alloc_init: dma_page @ 0x00ab2000 - 512 pages at 0x03e00000^M

hub 1-0:1.0: 1 port detected^M

NET: Registered protocol family 2^M

IP route cache hash table entries: 1024 (order: 0, 4096 bytes)^M

TCP established hash table entries: 2048 (order: 2, 16384 bytes)^M

TCP bind hash table entries: 2048 (order: 1, 8192 bytes)^M

TCP: Hash tables configured (established 2048 bind 2048)^M

TCP reno registered^M

NET: Registered protocol family 1^M

msgmni has been set to 102^M

io scheduler noop registered^M

io scheduler anticipatory registered (default)^M

io scheduler cfq registered^M

bf54x-lq043: FrameBuffer initializing...^M

bfin-otp: initialized^M

Serial: Blackfin serial driver^M

bfin-uart.1: ttyBF0 at MMIO 0xffc02000 (irq = 48) is a BFIN-UART^M

brd: module loaded^M

smsc911x: Driver version 2007-07-13.^M

eth0: SMSC911x MAC Address: 00:e0:22:fe:bf:4e^M

Driver 'sd' needs updating - please use bus_type methods^M

register bfin atapi driver^M

scsi0 : pata-bf54x^M

ata1: PATA max UDMA/66 irq 68^M

ata1.00: ATA-6: TOSHIBA MK4032GAX, AD101A, max UDMA/100^M

ata1.00: 78140160 sectors, multi 16: LBA48 ^M

ata1.00: configured for UDMA/66^M

blk_queue_max_hw_segments: set to minimum 1^M

scsi 0:0:0:0: Direct-Access     ATA      TOSHIBA MK4032GA AD10 PQ: 0 ANSI: 5^M

sd 0:0:0:0: [sda] 78140160 512-byte hardware sectors: (40.0 GB/37.2 GiB)^M

sd 0:0:0:0: [sda] Write Protect is off^M

sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA^M

sd 0:0:0:0: [sda] 78140160 512-byte hardware sectors: (40.0 GB/37.2 GiB)^M

sd 0:0:0:0: [sda] Write Protect is off^M

sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA^M

sda: sda1 sda2^M

sd 0:0:0:0: [sda] Attached SCSI disk^M

physmap platform flash device: 02000000 at 20000000^M

physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank^M

Intel/Sharp Extended Query Table at 0x010A^M

Intel/Sharp Extended Query Table at 0x010A^M

Intel/Sharp Extended Query Table at 0x010A^M

Intel/Sharp Extended Query Table at 0x010A^M

Intel/Sharp Extended Query Table at 0x010A^M

Using buffer write method^M

Using auto-unlock on power-up/resume^M

cfi_cmdset_0001: Erase suspend on write enabled^M

RedBoot partition parsing not available^M

Using physmap partition information^M

Creating 3 MTD partitions on "physmap-flash.0":^M

0x00000000-0x00040000 : "bootloader(nor)"^M

0x00040000-0x00440000 : "linux kernel(nor)"^M

0x00440000-0x01000000 : "file system(nor)"^M

BF5xx on-chip NAND FLash Controller Driver, Version 1.2 (c) 2007 Analog Devices, Inc.^M

bf5xx-nand bf5xx-nand.0: page_size=256, data_width=8, wr_dly=3, rd_dly=3^M

NAND device: Manufacturer ID: 0x20, Chip ID: 0xda (ST Micro NAND 256MiB 3,3V 8-bit)^M

Creating 2 MTD partitions on "NAND 256MiB 3,3V 8-bit":^M

0x00000000-0x00400000 : "linux kernel(nand)"^M

0x00400000-0x10000000 : "file system(nand)"^M

m25p80 spi0.1: m25p16 (2048 Kbytes)^M

Creating 2 MTD partitions on "m25p80":^M

0x00000000-0x00040000 : "bootloader(spi)"^M

0x00040000-0x00200000 : "linux kernel(spi)"^M

bfin-spi bfin-spi.0: Blackfin on-chip SPI Controller Driver, Version 1.0, regs_base@ffc00500, dma channel@4^M

bfin-spi bfin-spi.1: Blackfin on-chip SPI Controller Driver, Version 1.0, regs_base@ffc02300, dma channel@5^M

Initializing USB Mass Storage driver...^M

usbcore: registered new interface driver usb-storage^M

USB Mass Storage support registered.^M

input: bf54x-keys as /devices/platform/bf54x-keys/input/input0^M

bf54x-keys: Blackfin BF54x Keypad registered IRQ 76^M

rtc-bfin rtc-bfin: rtc core: registered rtc-bfin as rtc0^M

i2c /dev entries driver^M

i2c-bfin-twi i2c-bfin-twi.0: Blackfin BF5xx on-chip I2C TWI Contoller, regs_base@ffc00700^M

i2c-bfin-twi i2c-bfin-twi.1: Blackfin BF5xx on-chip I2C TWI Contoller, regs_base@ffc02200^M

bfin-wdt: initialized: timeout=20 sec (nowayout=0)^M

bfin-sdh bfin-sdh.0: unable to request DMA channel^M

bfin-sdh: probe of bfin-sdh.0 failed with error -16^M

usbcore: registered new interface driver usbhid^M

usbhid: v2.6:USB HID core driver^M

Advanced Linux Sound Architecture Driver Version 1.0.18rc3.^M

ASoC version 0.13.2^M

dma rx:0 tx:1, err irq:10, regs:ffc00800^M

AD1980 SoC Audio Codec^M

asoc: AC97 <-> bf5xx-ac97 mapping ok^M

ALSA device list:^M

  #0: bf5xx-board (AD1980)^M

TCP cubic registered^M

NET: Registered protocol family 17^M

rtc-bfin rtc-bfin: setting system clock to 2004-06-01 06:53:42 UTC (1086072822)^M

eth0: SMSC911x/921x identified at 0x24000000, IRQ: 175^M

eth0: link down^M

IP-Config: Complete:^M

     device=eth0, addr=10.100.4.50, mask=255.255.255.0, gw=10.100.4.174,^M

     host=bf548-ezkit, domain=, nis-domain=(none),^M

     bootserver=10.100.4.174, rootserver=10.100.4.174, rootpath=^M

Freeing unused kernel memory: 7844k freed^M

eth0: link up, 100Mbps, full-duplex, lpa 0x41E1^M

                           _____________________________________^M

        a8888b.           / Welcome to the uClinux distribution \^M

       d888888b.         /       _     _                         \^M

       8P"YP"Y88        /       | |   |_|            __  __ (TM)  |^M

       8|o||o|88  _____/        | |    _ ____  _   _ \ \/ /       |^M

       8'    .88       \        | |   | |  _ \| | | | \  /        |^M

       8`._.' Y8.       \       | |__ | | | | | |_| | /  \        |^M

      d/      `8b.       \      \____||_|_| |_|\____|/_/\_\       |^M

     dP   .    Y8b.       \   For embedded processors including   |^M

    d8:'  "  `::88b        \    the Analog Devices Blackfin      /^M

   d8"         'Y88b        \___________________________________/^M

  :8P    '      :888^M

   8a.   :     _a88P         For further information, check out:^M

._/"Yaa_:   .| 88P|            - http://blackfin.uclinux.org/^M

\    YP"    `| 8P  `.          - http://docs.blackfin.uclinux.org/^M

/     \.___.d|    .'           - http://www.uclinux.org/^M

`--..__)8888P`._.'  jgs/a:f    - http://www.analog.com/blackfin^M

^M

Have a lot of fun...^M

^M

^M

BusyBox v1.13.4 (2009-07-03 21:03:37 GMT) built-in shell (msh)^M

Enter 'help' for a list of built-in commands.^M

^M

root:/> versusb 1-1: new high speed USB device using musb_hdrc and address 2^M

iousb 1-1: configuration #1 chosen from 1 choice^M

scsi1 : SCSI emulation for USB Mass Storage devices^M

n^M

kernel:    Linux release 2.6.28.10-ADI-2009R1-svn6917, build #16 Sat Jul 4 07:45:00 GMT 2009^M

toolchain: bfin-uclinux-gcc release gcc version 4.1.2 (ADI svn)^M

user-dist: release svn-8427, build #278 Sat Jul 4 07:44:07 GMT 2009^M

root:/> successful boot attemptscsi 1:0:0:0: Direct-Access     SanDisk  U3 Cruzer Micro  6.51 PQ: 0 ANSI: 0 CCS^M

sd 1:0:0:0: [sdb] 2014271 512-byte hardware sectors: (1.03 GB/983 MiB)^M

sd 1:0:0:0: [sdb] Write Protect is off^M

sd 1:0:0:0: [sdb] Assuming drive cache: write through^M

sd 1:0:0:0: [sdb] 2014271 512-byte hardware sectors: (1.03 GB/983 MiB)^M

sd 1:0:0:0: [sdb] Write Protect is off^M

sd 1:0:0:0: [sdb] Assuming drive cache: write through^M

sdb: sdb1 sdb2^M

sd 1:0:0:0: [sdb] Attached SCSI removable disk^M

^M

root:/>

./dmacopy^M

TEST:  --- SRAM (L1 INST) <-> SDRAM w/4 bytes ---^M

PASS: dma_memcpy SDRAMx32[s] to SRAMx32[c]^M

PASS: dma_memcpy SRAMx32[c] to SDRAMx32[d]^M

PASS: dma_memcpy(dst, src) test case 1, memcmp result is 0^M

PASS: dma_memcpy SDRAMx16[s] to SRAMx16[c]^M

PASS: dma_memcpy SRAMx16[c] to SDRAMx16[d]^M

PASS: dma_memcpy(dst, src) test case 2, memcmp result is 0^M

PASS: dma_memcpy SDRAMx8[s] to SRAMx8[c]^M

PASS: dma_memcpy SRAMx8[c] to SDRAMx8[d]^M

PASS: dma_memcpy(dst, src) test case 3, memcmp result is 0^M

TEST:  --- SRAM (L1 INST) <-> SDRAM w/16 bytes ---^M

PASS: dma_memcpy SDRAMx32[s] to SRAMx32[c]^M

PASS: dma_memcpy SRAMx32[c] to SDRAMx32[d]^M

PASS: dma_memcpy(dst, src) test case 4, memcmp result is 0^M

PASS: dma_memcpy SDRAMx16[s] to SRAMx16[c]^M

PASS: dma_memcpy SRAMx16[c] to SDRAMx16[d]^M

PASS: dma_memcpy(dst, src) test case 5, memcmp result is 0^M

PASS: dma_memcpy SDRAMx8[s] to SRAMx8[c]^M

PASS: dma_memcpy SRAMx8[c] to SDRAMx8[d]^M

PASS: dma_memcpy(dst, src) test case 6, memcmp result is 0^M

TEST:  --- SRAM (L1 INST) <-> SDRAM w/4096 bytes ---^M

PASS: dma_memcpy SDRAMx32[s] to SRAMx32[c]^M

PASS: dma_memcpy SRAMx32[c] to SDRAMx32[d]^M

PASS: dma_memcpy(dst, src) test case 7, memcmp result is 0^M

PASS: dma_memcpy SDRAMx16[s] to SRAMx16[c]^M

PASS: dma_memcpy SRAMx16[c] to SDRAMx16[d]^M

PASS: dma_memcpy(dst, src) test case 8, memcmp result is 0^M

PASS: dma_memcpy SDRAMx8[s] to SRAMx8[c]^M

PASS: dma_memcpy SRAMx8[c] to SDRAMx8[d]^M

PASS: dma_memcpy(dst, src) test case 9, memcmp result is 0^M

TEST:  --- SRAM (L1 DATA) <-> SDRAM w/4 bytes ---^M

PASS: dma_memcpy SDRAMx32[s] to SRAMx32[c]^M

PASS: dma_memcpy(chk, src) test case 10, memcmp result is 0^M

PASS: dma_memcpy SRAMx32[c] to SDRAMx32[d]^M

PASS: dma_memcpy(dst, chk) test case 10, memcmp result is 0^M

PASS: dma_memcpy(dst, src) test case 10, memcmp result is 0^M

PASS: dma_memcpy SDRAMx16[s] to SRAMx16[c]^M

PASS: dma_memcpy(chk, src) test case 11, memcmp result is 0^M

PASS: dma_memcpy SRAMx16[c] to SDRAMx16[d]^M

PASS: dma_memcpy(dst, chk) test case 11, memcmp result is 0^M

PASS: dma_memcpy(dst, src) test case 11, memcmp result is 0^M

PASS: dma_memcpy SDRAMx8[s] to SRAMx8[c]^M

PASS: dma_memcpy(chk, src) test case 12, memcmp result is 0^M

PASS: dma_memcpy SRAMx8[c] to SDRAMx8[d]^M

PASS: dma_memcpy(dst, chk) test case 12, memcmp result is 0^M

PASS: dma_memcpy(dst, src) test case 12, memcmp result is 0^M

TEST:  --- SRAM (L1 DATA) <-> SDRAM w/16 bytes ---^M

PASS: dma_memcpy SDRAMx32[s] to SRAMx32[c]^M

PASS: dma_memcpy(chk, src) test case 13, memcmp result is 0^M

PASS: dma_memcpy SRAMx32[c] to SDRAMx32[d]^M

PASS: dma_memcpy(dst, chk) test case 13, memcmp result is 0^M

PASS: dma_memcpy(dst, src) test case 13, memcmp result is 0^M

PASS: dma_memcpy SDRAMx16[s] to SRAMx16[c]^M

PASS: dma_memcpy(chk, src) test case 14, memcmp result is 0^M

PASS: dma_memcpy SRAMx16[c] to SDRAMx16[d]^M

PASS: dma_memcpy(dst, chk) test case 14, memcmp result is 0^M

PASS: dma_memcpy(dst, src) test case 14, memcmp result is 0^M

PASS: dma_memcpy SDRAMx8[s] to SRAMx8[c]^M

PASS: dma_memcpy(chk, src) test case 15, memcmp result is 0^M

PASS: dma_memcpy SRAMx8[c] to SDRAMx8[d]^M

PASS: dma_memcpy(dst, chk) test case 15, memcmp result is 0^M

PASS: dma_memcpy(dst, src) test case 15, memcmp result is 0^M

TEST:  --- SRAM (L1 DATA) <-> SDRAM w/4096 bytes ---^M

PASS: dma_memcpy SDRAMx32[s] to SRAMx32[c]^M

PASS: dma_memcpy(chk, src) test case 16, memcmp result is 0^M

PASS: dma_memcpy SRAMx32[c] to SDRAMx32[d]^M

PASS: dma_memcpy(dst, chk) test case 16, memcmp result is 0^M

PASS: dma_memcpy(dst, src) test case 16, memcmp result is 0^M

PASS: dma_memcpy SDRAMx16[s] to SRAMx16[c]^M

PASS: dma_memcpy(chk, src) test case 17, memcmp result is 0^M

PASS: dma_memcpy SRAMx16[c] to SDRAMx16[d]^M

PASS: dma_memcpy(dst, chk) test case 17, memcmp result is 0^M

PASS: dma_memcpy(dst, src) test case 17, memcmp result is 0^M

PASS: dma_memcpy SDRAMx8[s] to SRAMx8[c]^M

PASS: dma_memcpy(chk, src) test case 18, memcmp result is 0^M

PASS: dma_memcpy SRAMx8[c] to SDRAMx8[d]^M

PASS: dma_memcpy(dst, chk) test case 18, memcmp result is 0^M

PASS: dma_memcpy(dst, src) test case 18, memcmp result is 0^M

TEST:  --- SRAM (L2) <-> SDRAM w/4 bytes ---^M

PASS: dma_memcpy SDRAMx32[s] to SRAMx32[c]^M

PASS: dma_memcpy(chk, src) test case 19, memcmp result is 0^M

PASS: dma_memcpy SRAMx32[c] to SDRAMx32[d]^M

PASS: dma_memcpy(dst, chk) test case 19, memcmp result is 0^M

PASS: dma_memcpy(dst, src) test case 19, memcmp result is 0^M

PASS: dma_memcpy SDRAMx16[s] to SRAMx16[c]^M

PASS: dma_memcpy(chk, src) test case 20, memcmp result is 0^M

PASS: dma_memcpy SRAMx16[c] to SDRAMx16[d]^M

PASS: dma_memcpy(dst, chk) test case 20, memcmp result is 0^M

PASS: dma_memcpy(dst, src) test case 20, memcmp result is 0^M

PASS: dma_memcpy SDRAMx8[s] to SRAMx8[c]^M

PASS: dma_memcpy(chk, src) test case 21, memcmp result is 0^M

PASS: dma_memcpy SRAMx8[c] to SDRAMx8[d]^M

PASS: dma_memcpy(dst, chk) test case 21, memcmp result is 0^M

PASS: dma_memcpy(dst, src) test case 21, memcmp result is 0^M

TEST:  --- SRAM (L2) <-> SDRAM w/16 bytes ---^M

PASS: dma_memcpy SDRAMx32[s] to SRAMx32[c]^M

PASS: dma_memcpy(chk, src) test case 22, memcmp result is 0^M

PASS: dma_memcpy SRAMx32[c] to SDRAMx32[d]^M

PASS: dma_memcpy(dst, chk) test case 22, memcmp result is 0^M

PASS: dma_memcpy(dst, src) test case 22, memcmp result is 0^M

PASS: dma_memcpy SDRAMx16[s] to SRAMx16[c]^M

PASS: dma_memcpy(chk, src) test case 23, memcmp result is 0^M

PASS: dma_memcpy SRAMx16[c] to SDRAMx16[d]^M

PASS: dma_memcpy(dst, chk) test case 23, memcmp result is 0^M

PASS: dma_memcpy(dst, src) test case 23, memcmp result is 0^M

PASS: dma_memcpy SDRAMx8[s] to SRAMx8[c]^M

PASS: dma_memcpy(chk, src) test case 24, memcmp result is 0^M

PASS: dma_memcpy SRAMx8[c] to SDRAMx8[d]^M

PASS: dma_memcpy(dst, chk) test case 24, memcmp result is 0^M

PASS: dma_memcpy(dst, src) test case 24, memcmp result is 0^M

TEST:  --- SRAM (L2) <-> SDRAM w/4096 bytes ---^M

PASS: dma_memcpy SDRAMx32[s] to SRAMx32[c]^M

PASS: dma_memcpy(chk, src) test case 25, memcmp result is 0^M

PASS: dma_memcpy SRAMx32[c] to SDRAMx32[d]^M

PASS: dma_memcpy(dst, chk) test case 25, memcmp result is 0^M

PASS: dma_memcpy(dst, src) test case 25, memcmp result is 0^M

PASS: dma_memcpy SDRAMx16[s] to SRAMx16[c]^M

PASS: dma_memcpy(chk, src) test case 26, memcmp result is 0^M

PASS: dma_memcpy SRAMx16[c] to SDRAMx16[d]^M

^M

^M

U-Boot 2008.10-svn1956 (ADI-2009R1-rc2) (Jul  2 2009 - 20:20:03)^M

^M

CPU:   ADSP bf548-0.0 (Detected Rev: 0.2) (parallel flash boot)^M

Board: ADI BF548 EZ-Kit board^M

       Support: http://blackfin.uclinux.org/^M

Clock: VCO: 525 MHz, Core: 525 MHz, System: 131.250 MHz^M

RAM:   64 MB^M

Flash: 16 MB^M

NAND:  256 MiB^M

In:    serial^M

Out:   serial^M

Err:   serial^M

Net:   MAC:   00:E0:22:FE:BF:4E^M

Hit any key to stop autoboot:  5 ^H^H^H

bfin>

--

 

Follow-ups

 

--- Robin Getz                                               2009-07-13 08:04:01

Why does it restart? If it is the watchdog - does the test pass when the

watchdog is not running? or does it hang forever?

 

-Robin

 

--- Vivi Li                                                  2009-07-13 22:03:41

Sorry for the confusion. It didn't hang, just reset into uboot.

 

--- Barry Song                                               2009-07-14 05:42:46

Definitely, the problem is not caused by dma operation to L2. In fact, the real

reason is writing L2 from CPU core.

If we delete memset to L2:

int _do_test(char *src_desc, char *dst_desc, char *src, char *dst, char *chk,

int size)

{

        static int test_num = 1;

        int ret = 0, i;

        void *ptr;

 

        memset(src, 's', size);

        memset(dst, 'd', size);

/*      if (!is_l1_inst(chk))

                memset(chk, 'c', size);

*/

...

}

All tests will pass!

I'd like to close this thread and start-up a new to describle the problem.

 

--- Mike Frysinger                                           2009-07-14 05:47:43

Jie has already looked into this i think.  ask him if he has any open tracker

items.

 

i dont see much point in opening a new tracker item ... this has history and

examples of how to reproduce already

 

--- Barry Song                                               2009-07-14 06:00:16

Ok. so there will be no new item.

Extra information is that L2 write-through is ok for memset, and write-back is

bad.

 

--- Sonic Zhang                                              2009-07-14 06:33:58

This must be a duplicated bug of bug 5192.

 

--- Mike Frysinger                                           2009-07-14 06:44:14

thanks

 

--- Barry Song                                               2009-07-17 05:29:46

Without enabling L2_DCACHE, means "# CONFIG_BFIN_L2_DCACHE is not

set".

It will fail too if memset L2. Only Write Through can work.

 

--- Graf Yang                                                2009-07-22 02:27:10

L2 Write Through also fail if runing several times.

 

I found we can not use hardware loop between SDRAM and L2 consecutively.

Adding SSYNC() or __builtin_bfin_ssync() between memset() will help.

 

When L2 not cached it's stable now.

I'm testing WB and WT...

 

 

--- Graf Yang                                                2009-07-22 03:59:35

If SDRAM is WB.

The SSYNC() is helpful for L2 no-cache and WT(AOW not set).

But useless for WB and WT(AOW set).

 

If SDRAM is WT(AOW set).

The SSYNC() is helpful for L2 no-cache and WT(AOW set or not set).

But useless for WB.

 

--- Graf Yang                                                2009-07-22 23:59:53

My BF548 0.2 run the test program with __builtin_bfin_ssync() all the night

(SDRAM WB, L2 unchached), and still alive.

 

--- Vivi Li                                                  2010-07-22 03:48:59

Close it.

 

 

 

    Files

    Changes

    Commits

    Dependencies

    Duplicates

    Associations

    Tags

 

File Name     File Type     File Size     Posted By

config.dmacopy    application/octet-stream    40724    Vivi Li

Attachments

Outcomes