[#4743] Dmacopy failed in BF537-STAMP

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[#4743] Dmacopy failed in BF537-STAMP

Submitted By: Vivi Li

Open Date

2008-12-23 01:57:41     Close Date

2009-01-20 01:55:43

Priority:

Medium High     Assignee:

Mike Frysinger

Status:

Closed     Fixed In Release:

N/A

Found In Release:

N/A     Release:

Category:

Kernel Functions     Board:

STAMP

Processor:

BF537     Silicon Revision:

Is this bug repeatable?:

Yes     Resolution:

Fixed

Uboot version or rev.:

    Toolchain version or rev.:

toolchain 4.1-2008_Dec_03

App binary format:

N/A     

Summary: Dmacopy failed in BF537-STAMP

Details:

 

Dmacopy failed in BF537-STAMP when copy from SRAM to SDRAM and kernel will reboot automatically.

 

Bellow is the log:

--

root:/> dmesg

Linux version 2.6.28-rc2-ADI-2009R1-pre-svn5898 (test@uclinux50-bf537-ad9960-ad1836) (gcc version 48

console [early_BFuart0] enabled

early printk enabled on early_BFuart0

Warning: limiting memory to 56MB due to hardware anomaly 05000263

Board Memory: 64MB

Kernel Managed Memory: 64MB

Memory map:

  fixedcode = 0x00000400-0x00000490

  text      = 0x00001000-0x0010b490

  rodata    = 0x0010b490-0x0015c980

  bss       = 0x0015c980-0x0016b468

  data      = 0x0016b468-0x0017c000

    stack   = 0x0017a000-0x0017c000

  init      = 0x0017c000-0x00487000

  available = 0x00487000-0x037ff000

  DMA Zone  = 0x03f00000-0x04000000

Hardware Trace Active and Enabled

Recovering from Watchdog event

Blackfin support (C) 2004-2008 Analog Devices, Inc.

Compiled for ADSP-BF537 Rev 0.2

Blackfin Linux support by   blackfin.uclinux.org/

Processor Speed: 500 MHz core clock and 100 MHz System Clock

boot memmap: 0000000000487000 - 00000000037ff000 (usable)

On node 0 totalpages: 14335

free_area_init_node: node 0, pgdat 00177e24, node_mem_map 0048c000

  DMA zone: 112 pages used for memmap

  DMA zone: 0 pages reserved

  DMA zone: 14223 pages, LIFO batch:3

  Normal zone: 0 pages used for memmap

  Movable zone: 0 pages used for memmap

NOMPU: setting up cplb tables

Instruction Cache Enabled for CPU0

Data Cache Enabled for CPU0 (write-through)

Built 1 zonelists in Zone order, mobility grouping off.  Total pages: 14223

Kernel command line: root=/dev/mtdblock0 rw earlyprintk=serial,uart0,57600 ip=10.100.4.50:10.100.4.f

Configuring Blackfin Priority Driven Interrupts

PID hash table entries: 256 (order: 8, 1024 bytes)

console handover: boot [early_BFuart0] -> real [ttyBF0]

Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)

Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)

Kernel managed physical pages: 14335

Memory available: 52124k/65536k RAM, (3116k init code, 1065k kernel code, 451k data, 1024k dma, 775)

Calibrating delay loop... 997.37 BogoMIPS (lpj=1994752)

Security Framework initialized

Mount-cache hash table entries: 512

Blackfin Scratchpad data SRAM: 4 KB

Blackfin L1 Data A SRAM: 16 KB (15 KB free)

Blackfin L1 Data B SRAM: 16 KB (16 KB free)

Blackfin L1 Instruction SRAM: 48 KB (41 KB free)

PDA for CPU0 reserved at 0015da68

net_namespace: 288 bytes

NET: Registered protocol family 16

Blackfin GPIO Controller

Blackfin DMA Controller

stamp_init(): registering device resources

NET: Registered protocol family 2

IP route cache hash table entries: 1024 (order: 0, 4096 bytes)

TCP established hash table entries: 2048 (order: 2, 16384 bytes)

TCP bind hash table entries: 2048 (order: 1, 8192 bytes)

TCP: Hash tables configured (established 2048 bind 2048)

TCP reno registered

NET: Registered protocol family 1

Setting up Blackfin MMR debugfs

msgmni has been set to 101

io scheduler noop registered

io scheduler anticipatory registered (default)

io scheduler cfq registered

Serial: Blackfin serial driver

bfin-uart.1: ttyBF0 at MMIO 0xffc00400 (irq = 18) is a BFIN-UART

brd: module loaded

bfin_mac_mdio: probed

bfin_mac: attached PHY driver [SMSC LAN83C185] (mii_bus:phy_addr=0:01, irq=-1, mdc_clk=2500000Hz(md)

bfin_mac bfin_mac.0: Blackfin on-chip Ethernet MAC driver, Version 1.1

bfin-spi bfin-spi.0: Blackfin on-chip SPI Controller Driver, Version 1.0, regs_base@ffc00500, dma c7

rtc-bfin rtc-bfin: rtc core: registered rtc-bfin as rtc0

bfin-wdt: initialized: timeout=20 sec (nowayout=0)

TCP cubic registered

NET: Registered protocol family 17

rtc-bfin rtc-bfin: setting system clock to 1970-01-01 08:14:54 UTC (29694)

IP-Config: Complete:

     device=eth0, addr=10.100.4.50, mask=255.255.255.0, gw=10.100.4.174,

     host=1, domain=, nis-domain=(none),

     bootserver=10.100.4.174, rootserver=10.100.4.174, rootpath=

Freeing unused kernel memory: 3116k freed

dma_alloc_init: dma_page @ 0x00483000 - 256 pages at 0x03f00000

PHY: 0:01 - Link is Up - 100/Full

root:/> ./dmacopy

TEST:  --- SRAM (L1 INST) <-> SDRAM w/4 bytes ---

PASS: dma_memcpy SDRAMx32[s] to SRAMx32[c]

PASS: dma_memcpy SRAMx32[c] to SDRAMx32[d]

PASS: dma_memcpy(dst, src) test case 1, memcmp result is 0

PASS: dma_memcpy SDRAMx16[s] to SRAMx16[c]

PASS: dma_memcpy SRAMx16[c] to SDRAMx16[d]

PASS: dma_memcpy(dst, src) test case 2, memcmp result is 0

PASS: dma_memcpy SDRAMx8[s] to SRAMx8[c]

PASS: dma_memcpy SRAMx8[c] to SDRAMx8[d]

FAIL: dma_memcpy(dst, src) test case 3, memcmp result is -7

        offsets differ: 1...2

TEST:  --- SRAM (L1 INST) <-> SDRAM w/16 bytes ---

 

 

U-Boot 1.1.6-svn1273 (ADI-2008R1.5) (Jul 21 2008 - 00:33:04)

 

CPU:   ADSP bf537-0.2 (Detected Rev: 0.2)

Board: ADI BF537 stamp board

       Support:   blackfin.uclinux.org/

Clock: VCO: 500 MHz, Core: 500 MHz, System: 100 MHz

RAM:   64 MB

Flash:  4 MB

In:    serial

Out:   serial

Err:   serial

Net:   Blackfin EMAC

MAC:   F2:B2:84:D7:34:26

Hit any key to stop autoboot:  0

bfin>

--

 

Follow-ups

 

--- Vivi Li                                                  2008-12-31 03:23:19

On some 537 borad, it may crash.

 

--

./dmacopy^M

TEST:  --- SRAM (L1 INST) <-> DaRtMaw 4abctcse---ss CPLB miss^M

- Used by the MMU to signal a CPLB miss on a data access.^M

Deferred Exception context^M

CURRENT PROCESS:^M

COMM=dmacopy PID=158^M

CPU = 0^M

TEXT = 0x00420040-0x004244e0        DATA = 0x004244e4-0x004250c4^M

BSS = 0x004250c4-0x004253a4  USER-STACK = 0x00426f84^M

^M

return address: [0x004219a2]; contents of:^M

0x00421980:  601b  549a  3212  e0a2  1008  c803  1800  9000 ^M

0x00421990:  9c01  0808  100f  0000  3298  0c42  1810  e0a2 ^M

0x004219a0:  2006 [9819] 9800  0808  1002  0000  5208  3299 ^M

0x004219b0:  0010  6fe0  3298  6c22  6fe3  2ff2  6000  3299 ^M

^M

SEQUENCER STATUS:               Not tainted^M

SEQSTAT: 00062026  IPEND: 0030  SYSCFG: 0006^M

  EXCAUSE   : 0x26^M

RETE: <0x00000000> { _do_one_initcall + 0xfffff000 }^M

RETN: <0x037aa000> /* kernel dynamic memory */^M

RETX: <0x00000480> /* Maybe fixed code section */^M

RETS: <0x00420388> [ dmacopy + 0x348 ]^M

PC  : <0x004219a2> [ dmacopy + 0x1962 ]^M

DCPLB_FAULT_ADDR: <0x65795473> /* kernel dynamic memory */^M

ICPLB_FAULT_ADDR: <0x004219a2> [ dmacopy + 0x1962 ]^M

^M

PROCESSOR STATE:^M

R0 : 00426e70    R1 : 65795473    R2 : 00000004    R3 : 0a0a0a0a^M

R4 : 00000004    R5 : 00000000    R6 : 00000041    R7 : ffffff82^M

P0 : 00426e70    P1 : 00426dce    P2 : 00000004    P3 : 65795473^M

P4 : 004250b8    P5 : 004244e4    FP : 00426e80    SP : 037a9f24^M

LB0: 004219ab    LT0: 004219a2    LC0: 00000004^M

LB1: 0042120d    LT1: 0042120c    LC1: 00000000^M

B0 : 00000000    L0 : 00000000    M0 : 00000000    I0 : 00424560^M

B1 : 00000000    L1 : 00000000    M1 : 00000000    I1 : 00426f88^M

B2 : 00000000    L2 : 00000000    M2 : 00000000    I2 : 00000000^M

B3 : 00000000    L3 : 00000000    M3 : 00000000    I3 : 00000000^M

A0.w: 00000000   A0.x: 00000000   A1.w: 00000000   A1.x: 00000000^M

USP : 00426e48  ASTAT: 02002002^M

^M

No trace since you do not have CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE enabled^M

^M

Userspace Stack^M

Stack info:^M

SP: [0x00426e48] <0x00426e48> [ dmacopy + 0x6e48 ]^M

FP: (0x00426e40)^M

Memory from 0x00426e40 to 00427000^M

00426e40:(00426e80)<0042037e>[004244e4] 00000050  ffffff82  00000041

00000000  00000004 ^M

00426e60: ffffffc0  00000052  00000000  65269467  0052c004  00426e70  0052c008

65795473 ^M

00426e80:(00426ec4)<0042076c> ffa01a05  0041e00d  00000001  004208f4

0052c00c  004248a4 ^M

00426ea0: 0041e00d  0052c00d  ffa01a05  00000fff  00000001  00000003  0041e00c

0052c00c ^M

00426ec0: ffa01a04 (00426f30)<0042096c> 00000000  004252f0  00001000

004249a0  00000001 ^M

00426ee0: 00000004  00000010  00001000  00010000  00012340  00022340  00032340

00042340 ^M

00426f00: 00054320  00323450  00000004  00000010  00001000  00010000  00012340

00000004 ^M

00426f20: 00000010  00001000  00000002  00000002 (00426f44)<004223cc>

00000000  00000000 ^M

00426f40: 00000000 (00000000)<001a3110> 004244e4  00470004  031603d8

00000000  031603bc ^M

00426f60: 0316036c  00000001  00000000  00000000  00000000  004244b8  004244ca

00000000 ^M

00426f80: 0047077f  00000001  00426fa5  00000000  00426faf  00426fb6  00426fc4

00426fe7 ^M

00426fa0: 00000000  642f2e00  6f63616d  48007970  3d454d4f  4853002f  3d4c4c45

6e69622f ^M

00426fc0: 0068732f  48544150  69622f3d  752f3a6e  622f7273  2f3a6e69  6e696273

73752f3a ^M

00426fe0: 62732f72  54006e69  3d4d5245  756e696c  2f2e0078  63616d64  0079706f

00000000 ^M

00427000: 93101000 ^M

Return addresses in stack:^M

   frame  1 : <0x0042037e> [ dmacopy + 0x33e ]^M

   frame  2 : <0x0042076c> [ dmacopy + 0x72c ]^M

   frame  3 : <0x0042096c> [ dmacopy + 0x92c ]^M

   frame  4 : <0x004223cc> [ dmacopy + 0x238c ]^M

   frame  5 : <0x001a3110> [ sh + 0x23110 ]^M

^M

PASS: dma_memcpy SDRAMx32[s] to SRAMx32[c]^M

PASS: dma_memcpy SRAMx32[c] to SDRAMx32[d]^M

PASS: dma_memcpy(dst, src) test case 1, memcmp result is 0^M

PASS: dma_memcpy SDRAMx16[s] to SRAMx16[c]^M

PASS: dma_memcpy SRAMx16[c] to SDRAMx16[d]^M

PASS: dma_memcpy(dst, src) test case 2, memcmp result is 0^M

PASS: dma_memcpy SDRAMx8[s] to SRAMx8[c]^M

PASS: dma_memcpy SRAMx8[c] to SDRAMx8[d]^M

FAIL: dma_memcpy(dst, src) test case 3, memcmp result is -7^M

        offsets differ: 1...2^M

TEST:  --- SRAM (L1 INST) <-> SDRAM w/16 bytes ---^M

PASS: dma_memcpy SDRAMx32[s] to SRAMx32[c]^M

PASS: dma_memcpy SRAMx32[c] to SDRAMx32[d]^M

PASS: dma_memcpy(dst, src) test case 4, memcmp result is 0^M

PASS: dma_memcpy SDRAMx16[s] to SRAMx16[c]^M

PASS: dma_memcpy SRAMx16[c] to SDRAMx16[d]^M

PASS: dma_memcpy(dst, src) test case 5, memcmp result is 0^M

PASS: dma_memcpy SDRAMx8[s] to SRAMx8[c]^M

PASS: dma_memcpy SRAMx8[c] to SDRAMx8[d]^M

FAIL: dma_memcpy(dst, src) test case 6, memcmp result is -103^M

        offsets differ: 0...11^M

TEST:  --- SRAM (L1 INST) <-> SDRAM w/4096 bytes ---^M

PASS: dma_memcpy SDRAMx32[s] to SRAMx32[c]^M

PASS: dma_memcpy SRAMx32[c] to SDRAMx32[d]^M

FAIL: dma_memcpy(dst, src) test case 7, memcmp result is -111^M

        offsets differ: 4...56 58...110 112...158 160...209 211...655 657...808

810...834 836...1114 1116...1153 1155...1158 1160...1181 1183...1397 1399...1732

1734...1809 1811...2393 2395...3101 3103...3135 3137...4095^M

PASS: dma_memcpy SDRAMx16[s] to SRAMx16[c]^M

PASS: dma_memcpy SRAMx16[c] to SDRAMx16[d]^M

FAIL: dma_memcpy(dst, src) test case 8, memcmp result is -15^M

        offsets differ: 2...4093^M

PASS: dma_memcpy SDRAMx8[s] to SRAMx8[c]^M

PASS: dma_memcpy SRAMx8[c] to SDRAMx8[d]^M

FAIL: dma_memcpy(dst, src) test case 9, memcmp result is -111^M

        offsets differ: 1...53 55...107 109...155 157...206 208...652 654...805

807...831 833...1111 1113...1150 1152...1155 1157...1178 1180...1394 1396...1729

1731...1806 1808...2390 2392...3098 3100...3132 3134...4094^M

FAIL: leading canary was killed {80,-126,65,0} vs {4,-64,82,0}!^M

Bus error^M

root:/> Hardware Trace:^M

   0 Target : <0x00004600> { _dump_bfin_trace_buffer + 0x0 }^M

     Source : <0x0003e29e> { _free_block + 0xee } CALL pcrel^M

   1 Target : <0x0003e29e> { _free_block + 0xee }^M

     Source : <0x0003e20c> { _free_block + 0x5c } IF !CC JUMP^M

   2 Target : <0x0003e204> { _free_block + 0x54 }^M

     Source : <0xffa00406> { _ex_dcplb_miss + 0x4a } RTX^M

   3 Target : <0xffa003e2> { _ex_dcplb_miss + 0x26 }^M

     Source : <0xffa010d0> { _dcplb_miss + 0xfc } RTS^M

   4 Target : <0xffa01028> { _dcplb_miss + 0x54 }^M

     Source : <0xffa0101c> { _dcplb_miss + 0x48 } IF !CC JUMP^M

   5 Target : <0xffa00ffe> { _dcplb_miss + 0x2a }^M

     Source : <0xffa010f4> { _dcplb_miss + 0x120 } JUMP.S^M

   6 Target : <0xffa010e4> { _dcplb_miss + 0x110 }^M

     Source : <0xffa00ffc> { _dcplb_miss + 0x28 } IF !CC JUMP^M

   7 Target : <0xffa00fd4> { _dcplb_miss + 0x0 }^M

     Source : <0xffa012b8> { _cplb_hdr + 0x1c } JUMP.L^M

   8 Target : <0xffa012b6> { _cplb_hdr + 0x1a }^M

     Source : <0xffa012a4> { _cplb_hdr + 0x8 } IF !CC JUMP^M

   9 Target : <0xffa0129c> { _cplb_hdr + 0x0 }^M

     Source : <0xffa003de> { _ex_dcplb_miss + 0x22 } CALL pcrel^M

  10 Target : <0xffa003bc> { _ex_dcplb_miss + 0x0 }^M

     Source : <0xffa003b2> { _ex_workaround_261 + 0x1a } IF CC JUMP^M

  11 Target : <0xffa00398> { _ex_workaround_261 + 0x0 }^M

     Source : <0xffa006d4> { _trap + 0x38 } JUMP (P4)^M

  12 Target : <0xffa006ba> { _trap + 0x1e }^M

     Source : <0xffa006b6> { _trap + 0x1a } IF !CC JUMP^M

  13 Target : <0xffa0069c> { _trap + 0x0 }^M

     Source : <0xffa0046a> { _bfin_return_from_exception + 0xe } RTX^M

  14 Target : <0xffa0045c> { _bfin_return_from_exception + 0x0 }^M

     Source : <0xffa003aa> { _ex_workaround_261 + 0x12 } IF !CC JUMP^M

  15 Target : <0xffa00398> { _ex_workaround_261 + 0x0 }^M

     Source : <0xffa006d4> { _trap + 0x38 } JUMP (P4)^M

BUG: failure at mm/slab.c:602/page_get_slab()!^M

Kernel panic - not syncing

--

 

--- Mike Frysinger                                           2009-01-09 06:47:46

should be fixed now

 

--- Vivi Li                                                  2009-01-20 01:55:43

OK now. Close it.

 

 

 

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