2011-10-21 05:32:06     question about sport & DMA

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2011-10-21 05:32:06     question about sport & DMA

Peter Lindner (AUSTRIA)

Message: 104071   


hello guys...


i've got a comprehensive question about using my blackfins sport with dma.


currently i'm using a CM-BF527 coremodule from bluetechnix.


on DR0PRI and DR0SEC i've got two 16-bit ADCs (AD7688) connected.


now i want do read values from both of them in my driver module.


my current sport configuration at the moment looks like this:




    rcr1 = RCKFE | LARFS | LRFS | RFSR | IRFS | IRCLK;

    rcr2 = 0x010F;

    rclkdiv = sclk / (2 * 1000000) - 1;


so i setup sport to read 16-bit values.




but now i'm not sure how to setup DMA. do i have to read one word with word-size 32-bit (because of the interleaved values from pri and sec channel in sport rx register)


or do i have to read two words with 16-bit word size?


my current DMA configuration (wich is not functioning at the moment) looks like this:




    unsigned int result;


    if (mutex_lock_interruptible(&dev->mutex))

        //return -ERESTARTSYS;


    invalidate_dcache_range((unsigned long)&result,(unsigned long)(&result+4));


    set_dma_start_addr(dev->dma_rx_chan, (unsigned long)&result);

    set_dma_x_count(dev->dma_rx_chan, 1);


    set_dma_config(dev->dma_rx_chan, WNR | RESTART | WDSIZE_32 | DI_EN);




    if (wait_for_completion_interruptible(&dev->c)) {

        printk("receive a signal to interrupt\n");



    printk ("value: %08X\n",result);






can anybody give me a hint, what i'm doing wrong here?


thank you for your help!


greets peter




2011-10-21 06:39:23     Re: question about sport & DMA

Martin Strubel (SWITZERLAND)

Message: 104074   


Hi Peter,


I'm not exactly sure whether 32 bit DMA would be appropriate there, I'd have to check the HRM myself. Anyhow, 16 bit DMA should work for your purpose (and it isn't less effective). Don't know if that helps as a starting point, but there's some DMA example setup in our standalone shell code:   section5.ch/dsp/blackfin/shell-1.1eval.tgz


For me, the best strategy was so far to try out things 'standalone' and then port them to uClinux using the appropriate kernel API equivalents (i.e. not using direct register access).




- Martin




2011-10-21 07:24:21     Re: question about sport & DMA

Peter Lindner (AUSTRIA)

Message: 104075   


hi martin...


you think, two 16-bit reads would be the right solution?


the thing i don't understand is... if i do two 16-bit reads on DMA... do i trigger two reads on SPORT???


greets peter




2011-10-21 10:55:48     Re: question about sport & DMA

Martin Strubel (SWITZERLAND)

Message: 104080   


If I remember right, the DMA width should just match the word width that the SPORT is configured with (padded to 16 or 32 bit), but the primary/secondary ports just mangle their 16 bit streams (in your case) into an internal FIFO the interleaved way. So you'd just DMA some chunk size that's a multiple of two in word size(!) and deal with the interleaved data. But it's been quite a while, I'd need to dig up some code and understand it, I'm sure one of the ADI experts has better insight there.


You could probably ask the detailed HW questions on the ez.analog.com forum, since this forum was announced to be merged with the latter. Seems ADI has realized after 7 years, that uClinux has gained significance not only among the power users.. Apology for this little personal opinion :-)


- Martin




2011-10-24 00:41:06     Re: question about sport & DMA

Sonic Zhang (CHINA)

Message: 104122   


Could move your question to our engineerzone as this forum will be replaced by it.






2011-10-24 05:32:18     Re: question about sport & DMA

Scott Jiang (CHINA)

Message: 104133   


Hi Peter,


The rx fifo size depends on the word length. In your case, I think you should set dma count to 2 and modify to 2.