2011-09-08 10:30:30     NAND / NAND Test Issues

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2011-09-08 10:30:30     NAND / NAND Test Issues

James Kosin (UNITED STATES)

Message: 103341   

 

Hi,

 

I'm having problems with the 'nandtest' application and reading/writting to the NAND layer... and have a simple question:

 

With the addition of caches and the like, is the interface to the NAND (address ranges) excluded from the caches specifically?  If not can they be excluded?  If they can't be excluded, then would setting the cache to disabled or even have it set to 'Write-Through' help or fix the problems?

 

Thanks for any insight.

 

James

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2011-09-11 21:06:14     Re: NAND / NAND Test Issues

Aaron Wu (CHINA)

Message: 103359   

 

Which CPU and NAND driver are you using? Generic driver or the NAND controller driver. The CPLB configurations determins if read/write acess is through cache across the DRAM memory address space but not that for the MMRs, you need to check the CPLB setting.

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2011-09-12 15:25:13     Re: NAND / NAND Test Issues

James Kosin (UNITED STATES)

Message: 103365   

 

Aaron,

 

BF537-0.3

 

plat_nand driver.

 

How do I check the CPLB setting?

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2011-09-13 23:16:39     Re: NAND / NAND Test Issues

Aaron Wu (CHINA)

Message: 103377   

 

Please refer to code arch/blackfin/kernel/cplb-nompu/cplbinit.c and the CPLB description in processor hardware user mannual. Actually I think you may elaborate the problem you met about NAND by starting a new topic.

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2011-09-15 14:47:02     Re: NAND / NAND Test Issues

James Kosin (UNITED STATES)

Message: 103399   

 

Aaron,

 

I'm getting ECC errors that seem to go away when I set the DCACHE to WT mode.  In WB mode I get frequent random errors on the NAND using the plat_nand driver for the kernel.

 

I'm still pulling my hair out one at a time, trying to find the issue or determine the cause of the problem.  I thought the issue was with the CPLB until I verified that it was correct.  This is a custom board that we are using ... so, I can't rule out hardware entirely other than to say many electrical engineers have looked at and reviewed the hardware and schematics.  My current work-around for the issue is to set the DCACHE to WT mode of operation ... and the random events causing the NAND to produce random ECC errors (causing me to loose the filesystem) seem to go away and I'm only left with the spuratic ECC correction.

 

James

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2011-09-15 22:35:40     Re: NAND / NAND Test Issues

Aaron Wu (CHINA)

Message: 103405   

 

Hi James, Thanks for the information, so looks like at least your work around works, please keep us updated for your further testing, if this issue also happens on the ADI board welcome to input a bug item in the tracking list.

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2011-09-16 16:35:59     Re: NAND / NAND Test Issues

James Kosin (UNITED STATES)

Message: 103417   

 

Aaron,

 

I've attached a few logs from several nandtest runs.

 

I thought there wasn't a pattern ... until I took a closer look.  You can see yourself too.

 

(1)  The pattern seems to suggest maybe that we are reading the data before R/B pin goes high, or

 

(2)  The ndelay() values are wrong... the delay.h file I have for the kernel says that the delay values and calculations were taken from another source tree to be used as an approximation.  Meaning maybe we aren't really delaying 100ns before the R/B polling.  I tried changing this value to 210 ... but, I still get the errors.

 

I'll do some more digging on Monday.

 

James

 

logs.zip

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2011-09-19 14:53:06     Re: NAND / NAND Test Issues

James Kosin (UNITED STATES)

Message: 103448   

 

Another possible fix, I've increased the ndelay() value to 400 (from the default 100) in nand_base.c.

 

My only guess here is that maybe the calulation for ndelay() is based on a WT cache architecture that breaks when in a WB architecture.  I tried a value of 210 thinking this was nseconds and with the documentation stating the calculations based in delay.h where approximate, I added a little to the maximum value the NAND I'm using has for Mode 0 accesses.

 

James

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2011-09-19 22:30:06     Re: NAND / NAND Test Issues

Aaron Wu (CHINA)

Message: 103452   

 

Hi James,

 

You may also take a look if the flush cache is properly called for WB mode in the generic Nand driver. Sounds like the cache is not flush in time to write to your device.

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2011-09-20 08:41:09     Re: NAND / NAND Test Issues

James Kosin (UNITED STATES)

Message: 103459   

 

Aaron,

 

The NAND is in a non-cacheable region.  So, flushing the cache shouldn't help the issue.

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