2011-07-12 03:50:15     SPI DMA CS inactive time

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2011-07-12 03:50:15     SPI DMA CS inactive time

Rob Maris (GERMANY)

Message: 102360   

 

While testing a 1MSPS ADC using DMA transfer, a too short SPI-CS inactive time for the ADC is observed (1/2 clock period). With tests, SPI clock 15 MHz is used.

 

According to datasheet, there is no way to specify idle time/clocks between transfer of any two 16-bit words. Any way out of this limitation?

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2011-07-12 18:50:23     Re: SPI DMA CS inactive time

Rob Maris (GERMANY)

Message: 102379   

 

I have been checking the ADC spec used in the blackfin oscilloscope application (AD7476). The minimum spec is 10 ns for CS inactive between two transfers - hence this fits with continuous blackfin SPI transfers (using drivers/char/bfin_spi_adc.c). I'd have to select another ADC which provides specs comparable to AD7476 in order to get proper SPI transfers.

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2011-07-12 22:13:24     Re: SPI DMA CS inactive time

Mike Frysinger (UNITED STATES)

Message: 102380   

 

you can set delay_usecs in the spi_transfer struct, but that's only in between transfers.  seems you want to do it in the middle of a transfer.  i dont think it's possible to use DMA and control the CS at the same time.

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