2011-06-27 11:02:12     VCO and clock dividers for BF537 (CM-BF537E)

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2011-06-27 11:02:12     VCO and clock dividers for BF537 (CM-BF537E)

Timothy Stotts (UNITED STATES)

Message: 101712   

 

I have a CM-BF537E board from BlueTechnix. The board has a BF537 processor. The processor oscillator is 25MHz.

 

How can I configure the kernel to operate the hardware at the 600 MHz (maximum speed) instead of 525 MHz, and what impact will this have on the SDRAM timing, etc.? I see the options under 'make menuconfig', but am unsure what to modify to increase the processor speed. Does this require a u-boot rebuild also?

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2011-06-27 11:10:20     VCO and clock dividers for BF537 (CM-BF537E)

Adam Rosenberg (UNITED STATES)

Message: 101713    Tim,

 

I tried using the kernel config to do this too but ultimately found it

was better to let uboot do the configurations. Find your config in

the includes folder and use 24 for the VCO. Here are my clock

settings:

 

/*

* Clock Settings

* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV

* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV

*/

/* CONFIG_CLKIN_HZ is any value in Hz */

#define CONFIG_CLKIN_HZ 25000000

/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */

/* 1 = CLKIN / 2 */

#define CONFIG_CLKIN_HALF 0

/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */

/* 1 = bypass PLL */

#define CONFIG_PLL_BYPASS 0

/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */

/* Values can range from 0-63 (where 0 means 64) */

#define CONFIG_VCO_MULT 24 /* 20 = 500Mhz 24 = 600Mhz */

/* CCLK_DIV controls the core clock divider */

/* Values can be 1, 2, 4, or 8 ONLY */

#define CONFIG_CCLK_DIV 1

/* SCLK_DIV controls the system clock divider */

/* Values can range from 1-15 */

#define CONFIG_SCLK_DIV 5 /* at 500Mhz 4 = 125Mhz 5=100Mhz at 500Mhz

5 = 120Mhz*/

 

rebuild your uboot and load it into flash

 

-Adam

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2011-06-27 13:05:30     Re: VCO and clock dividers for BF537 (CM-BF537E)

Mike Frysinger (UNITED STATES)

Message: 101714   

 

you will need to recompute the SDRAM timings yourself.  please consult this page:

  docs.blackfin.uclinux.org/doku.php?id=bfin:sdram

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