2011-05-29 05:21:44     ppi_test, consecutive write problem

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2011-05-29 05:21:44     ppi_test, consecutive write problem

rifat tursen (UNITED STATES)

Message: 100927   

 

Hello,

 

I have interfaced BF537 Stamp with an FPGA card and I am trying to utilize the PPI interface so that Blackfin and FPGA can communicate with each other.  I have written a module for the FPGA and use   " /blkfin-test/ppi-test " on Blackfin to test the interface.

 

I can do consecutive writes to FPGA from Blackfin without problems but I can not do consecutive writes to Blackfin from FPGA. What's more interesting is that if I have a pattern like  " read frm Blackfin /  write to Blackfin " everything works fine. Here is the output of ppi-test output

 

 

 

----------   Read frm BF537,  Write to BF537,  Write to BF537 --------------------------------

 

root:/home> ./ppi_rx_tx master

fd(3) = open(/dev/ppi)

Enter Line length (default = 512):

512

Enter number of lines (default = 16):

16

beMaster()

Setting up master...new gImageSize( 2C38004 ) = 0x4000 (16384)

Master set up complete...further input is transmited to slave

Enter fill pattern [CcQqRrTtVvHh?]:  C

fillBuffer(2C38004, 512, 16, 'C', 0x0)

   1    2    3    4    5    6    7    8    9    A    B    C    D    E    F   10

   1    2    3    4    5    6    7    8    9    A    B    C    D    E    F   10

   1    2    3    4    5    6    7    8    9    A    B    C    D    E    F   10

   1    2    3    4    5    6    7    8    9    A    B    C    D    E    F   10

   1    2    3    4    5    6    7    8    9    A    B    C    D    E    F   10

   1    2    3    4    5    6    7    8    9    A    B    C    D    E    F   10

   1    2    3    4    5    6    7    8    9    A    B    C    D    E    F   10

   1    2    3    4    5    6    7    8    9    A    B    C    D    E    F   10

   1    2    3    4    5    6    7    8    9    A    B    C    D    E    F   10

....

Enter fill pattern [CcQqRrTtVvHh?]:  ^C                  I check that on the FPGA, data is received correctly

 

 

root:/home> ./ppi_rx_tx slave                                   1st write,  Received data from FPGA is correct

fd(3) = open(/dev/ppi)                                                         

Enter Line length (default = 512):                                             

512                                                                            

Enter number of lines (default = 16):                                          

16                                                                             

beSlave()                                                                      

new gImageSize( 2C38004 ) = 0x4000 (16384)                                     

Setting up slave...to read 16384 bytesSlave set up complete...following output .

   0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F

   0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F

   0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F

   0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F

   0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F

   0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F

   0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F

   0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F

   0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F

....

 

^C                                                                             

 

root:/home> ./ppi_rx_tx slave                                           Second write fails,   FPGA did actually send data.

 

fd(3) = open(/dev/ppi)                                                         

 

Enter Line length (default = 512):                                             

 

512                                                                            

 

Enter number of lines (default = 16):                                          

 

16                                                                             

 

beSlave()                                                                      

 

new gImageSize( 2C38004 ) = 0x4000 (16384)                                     

 

Setting up slave...to read 16384 bytesSlave set up complete...following output .

 

   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

 

   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

 

   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

 

   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

 

   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

 

   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

 

   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

 

   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

 

   0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

 

....

 

 

 

I have asked a friend of mine that has a program called Chipscope frm Xilinx to check the output of the FPGA and he confirmed that FPGA sends the control and data signals correctly at every write.

 

I have set the PPI interface such that Lvalid, Fvalid signals are supplied by FPGA for both write and read accesses. Field signal is kept at Ground level. Data width is 16 bits. Below are the IOCTL commands for slave and master config.

 

ppiMasterTable2D[] = {

 

    { CMD_PPI_SKIPPING, CFG_PPI_SKIP_DISABLE },

 

    { CMD_PPI_SKIP_ODDEVEN, CFG_PPI_SKIP_ODD },

 

    { CMD_PPI_DATALEN, CFG_PPI_DATALEN_16 },

 

//    { CMD_PPI_DATALEN, CFG_PPI_DATALEN_14 },

 

    { CMD_PPI_CLK_EDGE, CFG_PPI_CLK_EDGE_RISE },

 

    { CMD_PPI_TRIG_EDGE, CFG_PPI_TRIG_EDGE_RISE },

 

    { CMD_PPI_XFR_TYPE, CFG_PPI_XFR_TYPE_NON646 },

 

//    { CMD_PPI_XFR_TYPE, CFG_PPI_XFR_TYPE_SYNC },

 

    { CMD_PPI_PORT_CFG, CFG_PPI_PORT_CFG_SYNC23 },

 

    { CMD_PPI_SET_DIMS, CFG_PPI_DIMS_2D },

 

    { CMD_PPI_DELAY, 0 },

 

    { CMD_PPI_GEN_FS12_TIMING_ON_WRITE, 0 },

 

//    { CMD_PPI_GEN_FS12_TIMING_ON_WRITE, 1 },

 

    { 0, 0 }

 

},

 

ppiSlaveTable2D[] = {

    { CMD_PPI_SKIPPING, CFG_PPI_SKIP_DISABLE },

    { CMD_PPI_SKIP_ODDEVEN, CFG_PPI_SKIP_ODD },

    { CMD_PPI_DATALEN, CFG_PPI_DATALEN_16 },

//    { CMD_PPI_DATALEN, CFG_PPI_DATALEN_14 },

    { CMD_PPI_CLK_EDGE, CFG_PPI_CLK_EDGE_RISE },

    { CMD_PPI_TRIG_EDGE, CFG_PPI_TRIG_EDGE_RISE },

    { CMD_PPI_XFR_TYPE, CFG_PPI_XFR_TYPE_NON646 },

    { CMD_PPI_PORT_CFG, CFG_PPI_PORT_CFG_XSYNC23 },

    { CMD_PPI_SET_DIMS, CFG_PPI_DIMS_2D },

    { CMD_PPI_DELAY, 0 },

//    { CMD_PPI_DELAY, 1 },

    { 0, 0 }

};

 

 

 

I would be happy if you can guide me for finding a solution to this problem.

 

Thank you very much for your help

 

Rifat

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2011-06-10 06:28:21     Re: ppi_test, consecutive write problem

Aaron Wu (CHINA)

Message: 101179   

 

Noticed that your ppiMasterTable2D  and ppiSlaveTable2D setting is a little different with the ADI original setting, what the result would be if you use the default setting? Thanks.

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